:86(:6X$mediatek,mt8173-evbmediatek,mt8173 +!7MediaTek MT8173 evaluation boardcpus+cpu-mapcluster0core0=core1=cluster1core0=core1=cpu@0Acpuarm,cortex-a53MQpsci_o~cpu@1Acpuarm,cortex-a53MQpsci_~cpu@100Acpuarm,cortex-a57MQpsci_o~cpu@101Acpuarm,cortex-a57MQpsci_~idle-statespscicpu-sleep-0arm,idle-state@~psci arm,psciXsmcoscillator@0 fixed-clock+clk26m~  oscillator@1 fixed-clock}+clk32koscillator@2 fixed-clock+cpum_cktimerarm,armv8-timer 0>   soc+ simple-busIclock-controller@10000000mediatek,mt8173-topckgenM~  power-controller@10001000 mediatek,mt8173-infracfgsysconMP~  power-controller@10003000mediatek,mt8173-pericfgsysconM0P~  syscfg_pctl_a@10005000%mediatek,mt8173-pctl-a-syscfgsysconMP~pinctrl@0x10005000mediatek,mt8173-pinctrlM]r$>~  i2c0~pins1-.i2c1~pins1}~i2c2~pins1+,i2c3~pins1jki2c4~pins1i2c6~pins1demmc0default~pins_cmd_dat$9:;<=>?@Bpins_clkApins_rstDmmc1default~pins_cmd_datIJKLNfpins_clkMpins_insertmmc0~pins_cmd_dat$9:;<=>?@Bepins_clkAepins_rstDmmc1~pins_cmd_datIJKLNfpins_clkMfspi0~pins_spiEFGHscpsys@10006000mediatek,mt8173-scpsysM`& U X i-mfgmmvencvenc_lt9 ~watchdog@10007000(mediatek,mt8173-wdtmediatek,mt6589-wdtMppwrap@1000d000mediatek,mt8173-pwrapMBpwrap >L Spwrap&  -spiwrapmt6397mediatek,mt6397 > mt6397regulatormediatek,mt6397-regulatorbuck_vpca15 _buck_vpca15tvpca15 `p0buck_vpca7 _buck_vpca7tvpca7 `p0sbuck_vsramca15_buck_vsramca15 tvsramca15 `p0buck_vsramca7_buck_vsramca7 tvsramca7 `p0buck_vcore _buck_vcoretvcore `p0buck_vgpu _buck_vgputvgpu `p0sbuck_vdrm _buck_vdrmtvdrmO\0buck_vio18 _buck_vio18tvio18 6`0~ldo_vtcxo _ldo_vtcxotvtcxoldo_va28 _ldo_va28tva28ldo_vcama _ldo_vcamatvcama`*ldo_vio28 _ldo_vio28tvio28ldo_vusb _ldo_vusbtvusbldo_vmc_ldo_vmctvmcw@2Z~ldo_vmch _ldo_vmchtvmch-2Z~ldo_vemc3v3 _ldo_vemc3v3 tvemc_3v3-2Z~ldo_vgp1 _ldo_vgp1tvcamd2Zldo_vgp2 _ldo_vgp2tvcamioB@2Zldo_vgp3 _ldo_vgp3tvcamafO2Zldo_vgp4 _ldo_vgp4tvgp4O2Zldo_vgp5 _ldo_vgp5tvgp5O-ldo_vgp6 _ldo_vgp6tvgp6O2Zldo_vibr _ldo_vibrtvibr 2Zintpol-controller@10200620.mediatek,mt8173-sysirqmediatek,mt6577-sysirq M  ~clock-controller@10209000mediatek,mt8173-apmixedsysM interrupt-controller@10220000 arm,gic-400 @M"" "@ "`  > ~serial@11002000*mediatek,mt8173-uartmediatek,mt6577-uartM  >S& $  -baudbusokayserial@11003000*mediatek,mt8173-uartmediatek,mt6577-uartM0 >T& %  -baudbus disabledserial@11004000*mediatek,mt8173-uartmediatek,mt6577-uartM@ >U& &  -baudbus disabledserial@11005000*mediatek,mt8173-uartmediatek,mt6577-uartMP >V& '  -baudbus disabledi2c@11007000mediatek,mt8173-i2c Mpp >L&   -maindma default+ disabledi2c@11008000mediatek,mt8173-i2c Mp >M&   -maindma default+okayda9211@68 dlg,da9211MhregulatorsBUCKAtVBUCKA `0!8C#'BUCKBtVBUCKB `0!8-'i2c@11009000mediatek,mt8173-i2c Mp >N&   -maindma default+ disabledspi@1100a000mediatek,mt8173-spi+M >n& 4 \ -parent-clksel-clkspi-clkokay defaultOi2c@11010000mediatek,mt8173-i2c Mp >O&   -maindma default+ disabledi2c@11011000mediatek,mt8173-i2c Mp >P&   -maindma default+ disabledi2c@11013000mediatek,mt8173-i2c M0p >R& #  -maindma default+ disabledaudio-controller@11220000mediatek,mt8173-afe-pcmM" >cP&  d e y  b-infra_sys_audio_clktop_pdn_audiotop_pdn_aud_intbusbck0bck1i2s0_mi2s1_mi2s2_mi2s3_mi2s3_bq m n  mmc@11230000(mediatek,mt8173-mmcmediatek,mt8135-mmcM# >G&  _ -sourcehclkokay defaultstate_uhsmmc@11240000(mediatek,mt8173-mmcmediatek,mt8135-mmcM$ >H&  R -sourcehclkokay defaultstate_uhs  mmc@11250000(mediatek,mt8173-mmcmediatek,mt8135-mmcM% >I&  R -sourcehclk disabledmmc@11260000(mediatek,mt8173-mmcmediatek,mt8135-mmcM& >J&  u -sourcehclk disabledclock-controller@14000000mediatek,mt8173-mmsyssysconMclock-controller@15000000mediatek,mt8173-imgsyssysconMclock-controller@16000000mediatek,mt8173-vdecsyssysconMclock-controller@18000000mediatek,mt8173-vencsyssysconMclock-controller@19000000!mediatek,mt8173-vencltsyssysconMaliases/soc/serial@11002000"/soc/serial@11003000*/soc/serial@110040002/soc/serial@11005000memory@40000000AmemoryM@chosen compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodcpu-idle-states#cooling-cellslinux,phandleentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramcpu_suspendcpu_offcpu_on#clock-cellsclock-frequencyclock-output-namesinterruptsranges#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxbias-disableinput-enablebias-pull-upbias-pull-downdrive-strength#power-domain-cellsclocksclock-namesinfracfgreg-namesresetsreset-namesregulator-compatibleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-enable-ramp-delaystatusclock-divpinctrl-namespinctrl-0regulator-min-microampregulator-max-microampmediatek,pad-selectpower-domainsassigned-clocksassigned-clock-parentspinctrl-1bus-widthmax-frequencycap-mmc-highspeedvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr25cd-gpiosserial0serial1serial2serial3