H|(Z4Foundation-v8A$arm,foundation-aarch64arm,vexpress"1chosenaliases#=/smb/iofpga@3,00000000/uart@090000#E/smb/iofpga@3,00000000/uart@0a0000#M/smb/iofpga@3,00000000/uart@0b0000#U/smb/iofpga@3,00000000/uart@0c0000cpus"1cpu@0]cpu arm,armv8i mspin-table{cpu@1]cpu arm,armv8i mspin-table{cpu@2]cpu arm,armv8i mspin-table{cpu@3]cpu arm,armv8i mspin-table{l2-cache0cachememory@80000000]memory iinterrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gic"@i,, ,@ ,`   timerarm,armv8-timer0   pmuarm,armv8-pmuv30<=>?smbarm,vexpress,v2m-p1simple-busrs1"1x  ?            !!""##$$%%&&''(())**ethernet@2,02000000smsc,lan91c111 iclk24mhz fixed-clock'n6 4v2m:clk24mhzrefclk1mhz fixed-clock'B@4v2m:refclk1mhzrefclk32khz fixed-clock'4v2m:refclk32khziofpga@3,00000000arm,amba-bussimple-bus"1 sysreg@010000arm,vexpress-sysregiuart@090000arm,pl011arm,primecelli GNuartclkapb_pclkuart@0a0000arm,pl011arm,primecelli GNuartclkapb_pclkuart@0b0000arm,pl011arm,primecelli GNuartclkapb_pclkuart@0c0000arm,pl011arm,primecelli GNuartclkapb_pclkvirtio_block@0130000 virtio,mmioi* modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3device_typeregenable-methodcpu-release-addrnext-level-cachelinux,phandle#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyarm,v2m-memory-maprangesinterrupt-map-maskinterrupt-map#clock-cellsclock-output-namesclocksclock-names