~8P(.7marvell,berlin4ct-dmpmarvell,berlin4ctmarvell,berlin +7Marvell BG4CT DMP boardaliases=/soc/apb@fc0000/uart@d000psci arm,psci-0.2Esmccpus+cpu@0arm,cortex-a53arm,armv8LcpuX\pscijpcpu@1arm,cortex-a53arm,armv8LcpuX\pscijpcpu@2arm,cortex-a53arm,armv8LcpuX\pscijpcpu@3arm,cortex-a53arm,armv8LcpuX\pscijposc fixed-clockx}x@jppmuarm,armv8-pmuv30timerarm,armv8-timer0   soc simple-bus+interrupt-controller@901000 arm,gic-400 X @ `   jpapb@e80000 simple-bus+  gpio@0400snps,dw-apb-gpioX+gpio-port@0snps,dw-apb-gpio-port Xgpio@0800snps,dw-apb-gpioX+gpio-port@1snps,dw-apb-gpio-port Xgpio@0c00snps,dw-apb-gpioX +gpio-port@2snps,dw-apb-gpio-port Xgpio@1000snps,dw-apb-gpioX+gpio-port@3snps,dw-apb-gpio-port Xinterrupt-controller@3800snps,dw-apb-ictlX80  jpapb@fc0000 simple-bus+  interrupt-controller@1000snps,dw-apb-ictlX0  jpgpio@8000snps,dw-apb-gpioX+gpio-port@4snps,dw-apb-gpio-port Xgpio@9000snps,dw-apb-gpioX+gpio-port@5snps,dw-apb-gpio-port Xuart@d000snps,dw-apb-uartX okaychosen"serial0:115200n8memoryLmemoryX compatibleinterrupt-parent#address-cells#size-cellsmodelserial0methoddevice_typeregenable-methodlinux,phandle#clock-cellsclock-frequencyinterruptsinterrupt-affinityranges#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellssnps,nr-gpiosclocksreg-shiftstatusstdout-path