tR8mX(m  ,ZII i.MX8MQ Ultra Zest Board22zii,imx8mq-ultra-zestzii,imx8mq-ultrafsl,imx8mqaliases"=/soc@0/bus@30000000/gpio@30200000"C/soc@0/bus@30000000/gpio@30210000"I/soc@0/bus@30000000/gpio@30220000"O/soc@0/bus@30000000/gpio@30230000"U/soc@0/bus@30000000/gpio@30240000![/soc@0/bus@30800000/i2c@30a20000!`/soc@0/bus@30800000/i2c@30a30000!e/soc@0/bus@30800000/i2c@30a40000!j/soc@0/bus@30800000/i2c@30a50000$o/soc@0/bus@30800000/serial@30860000$w/soc@0/bus@30800000/serial@30890000$/soc@0/bus@30800000/serial@30880000$/soc@0/bus@30800000/serial@30a60000!/soc@0/bus@30800000/spi@30820000!/soc@0/bus@30800000/spi@30830000!/soc@0/bus@30800000/spi@30840000/bitbang-mdio(/soc@0/bus@30800000/i2c@30a30000/rtc@68clock-ckil 2fixed-clockckilclock-osc-25m 2fixed-clock}x@osc_25mclock-osc-27m 2fixed-clockosc_27mclock-ext1 2fixed-clockk@ clk_ext1clock-ext2 2fixed-clockk@ clk_ext2clock-ext3 2fixed-clockk@ clk_ext3clock-ext4 2fixed-clockk@ clk_ext4cpus cpu@0cpu2arm,cortex-a53l psci*>M Yspeed_gradejcpu@1cpu2arm,cortex-a53l psci*>j cpu@2cpu2arm,cortex-a53l psci*>j cpu@3cpu2arm,cortex-a53l psci*>j l2-cache02cacheopp-table2operating-points-v2uopp-800000000/ Iopp-1000000000; Iopp-1300000000M|mB@ Iopp-1500000000Yh/B@Ipmu2arm,cortex-a53-pmu  psci 2arm,psci-1.0smcthermal-zonescpu-thermal tripscpu-alert8!passive cpu-crit_! criticalcooling-mapsmap0, 01 gpu-thermal tripsgpu-crit_! criticalvpu-thermal tripsvpu-crit_! criticaltimer2arm,armv8-timer0   @soc@0 2simple-bus W>^@@bus@300000002fsl,imx8mq-aips-bussimple-bus  W00@gpio@302000002fsl,imx8mq-gpiofsl,imx35-gpio0 @Aiy 'gpio@302100002fsl,imx8mq-gpiofsl,imx35-gpio0!BCiy(/gpio@302200002fsl,imx8mq-gpiofsl,imx35-gpio0"DEiy=default!usb-emulation usb-emulationusb-mode1  usb-mode1usb-pwr usb-pwr-ctrl-en-nusb-mode2  usb-mode2gpio@302300002fsl,imx8mq-gpiofsl,imx35-gpio0#FGiyW gpio@302400002fsl,imx8mq-gpiofsl,imx35-gpio0$HIiywtmu@302600002fsl,imx8mq-tmu0& 1 &Ha@#)/5=CKQW _ g o#+3;CKU] g p#-7AKWco!-9ES_q/ watchdog@302800002fsl,imx8mq-wdtfsl,imx21-wdt0( N Edisabledwatchdog@302900002fsl,imx8mq-wdtfsl,imx21-wdt0) O Edisabledwatchdog@302a00002fsl,imx8mq-wdtfsl,imx21-wdt0*   Edisabledsdma@302c00002fsl,imx8mq-sdmafsl,imx7d-sdma0, gLipgahbXcimx/sdma/sdma-imx7d.biniomuxc@303300002fsl,imx8mq-iomuxc03fec1grp|hl#x|t1fec1phyresetgrp|Hgpio3hoggrp`| $(i2c1grp0||@@i2c2grp0|@ @"i2c3grp0|$@(@#i2c4grp0|,@0@%bitbangmdiogrp0|\D`dGpcie0grp0|L$f4Cpcie1grp0|P(f@Eregarmgrp|4Lregusdhc2grp|TAJswitchgrp|dA3tsgrp0|TX&uart1grp0|4I8Iuart2grp0|<I@Iucs1002grp0|8A<A usbhubgrp|XA$usdhc1grp |  $(,40(usdhc1-100grp |  $(,40)usdhc1-200grp |  $(,40*usdhc2grp|<@DHLP8,usdhc2-100grp|<@DHLP8-usdhc2-200grp|<@DHLP8.syscon@30340000=2fsl,imx8mq-iomuxc-gprfsl,imx6q-iomuxc-gprsysconsimple-mfd04mux-controller 2mmio-mux4ocotp-ctrl@303500002fsl,imx8mq-ocotpsyscon05 speed-grade@10syscon@303600002fsl,imx8mq-anatopsyscon06 1snvs@30370000#2fsl,sec-v4.0-monsysconsimple-mfd07snvs-rtc-lp2fsl,sec-v4.0-mon-rtc-lp4 Lsnvs-rtc Edisabledsnvs-powerkey2fsl,sec-v4.0-pwrkey t Edisabledclock-controller@303800002fsl,imx8mq-ccm08UV9Lckilosc_25mosc_27mclk_ext1clk_ext2clk_ext3clk_ext4reset-controller@303900002fsl,imx8mq-srcsyscon09Bgpc@303a00002fsl,imx8mq-gpc0: Wpgc power-domain@0power-domain@1Apower-domain@2<power-domain@3?power-domain@4power-domain@5 fop:power-domain@6power-domain@7power-domain@8power-domain@9 power-domain@a bus@304000002fsl,imx8mq-aips-bussimple-bus  W0@0@@pwm@306600002fsl,imx8mq-pwmfsl,imx27-pwm0f QLipgper  Edisabledpwm@306700002fsl,imx8mq-pwmfsl,imx27-pwm0g RLipgper  Edisabledpwm@306800002fsl,imx8mq-pwmfsl,imx27-pwm0h SLipgper  Edisabledpwm@306900002fsl,imx8mq-pwmfsl,imx27-pwm0i TLipgper  Edisabledtimer@306a00002nxp,sysctr-timer0j /Lperbus@308000002fsl,imx8mq-aips-bussimple-bus W00@spi@30820000 !2fsl,imx8mq-ecspifsl,imx51-ecspi0 Lipgper Edisabledspi@30830000 !2fsl,imx8mq-ecspifsl,imx51-ecspi0  Lipgper Edisabledspi@30840000 !2fsl,imx8mq-ecspifsl,imx51-ecspi0 !Lipgper Edisabledserial@308600002fsl,imx8mq-uartfsl,imx6q-uart0 LipgperEokaydefaultserial@308800002fsl,imx8mq-uartfsl,imx6q-uart0 Lipgper Edisabledserial@308900002fsl,imx8mq-uartfsl,imx6q-uart0 LipgperEokaydefaultrave-sp2zii,rave-sp-rdu2B@ watchdog2zii,rave-sp-watchdogbacklight2zii,rave-sp-backlightpwrbutton2zii,rave-sp-pwrbuttoneeprom@a32zii,rave-sp-eeprom@ %dds-eepromeeprom@a42zii,rave-sp-eeprom@  %main-eepromsai@308b000052fsl,imx8mq-sai0 ` Lbusmclk1mclk2mclk3 F  Krxtx Edisabledcrypto@30900000 2fsl,sec-v4.0 0 W0 [t Laclkipgjr@10002fsl,sec-v4.0-job-ring ijr@20002fsl,sec-v4.0-job-ring  jjr@30002fsl,sec-v4.0-job-ring0 rdphy@30a003002fsl,imx8mq-mipi-dphy0Lphy_refUe%|n6 Edisabledi2c@30a200002fsl,imx8mq-i2cfsl,imx21-i2c0 # Eokaydefaultcharger@322microchip,ucs1002default 2! a_detalert=i2c@30a300002fsl,imx8mq-i2cfsl,imx21-i2c0 $ Eokaydefault"pmic@8 2fsl,pfuze100regulatorssw1ab sw1c sw2sw3ab sw4w@w@+swbstLK@N0vsnvsB@-vrefddrvgen1 5vgen2 Pvgen3"vgen4˨8vgen5.7P(vgen6w@2Zeeprom@54 2atmel,24c128Trtc@682dallas,ds1341hi2c@30a400002fsl,imx8mq-i2cfsl,imx21-i2c0 % Eokaydefault#usbhub@2c2microchip,usb2513bdefault$, !i2c@30a500002fsl,imx8mq-i2cfsl,imx21-i2c0 & Eokaydefault%touchscreen@4a2atmel,maxtouchdefault&J' serial@30a600002fsl,imx8mq-uartfsl,imx6q-uart0 Lipgper Edisabledmmc@30b40000!2fsl,imx8mq-usdhcfsl,imx7d-usdhc0 i LipgahbperU|ׄ!Eokay"defaultstate_100mhzstate_200mhz(+)5*?+LZ`mmc@30b50000!2fsl,imx8mq-usdhcfsl,imx7d-usdhc0 i Lipgahbper!Eokay"defaultstate_100mhzstate_200mhz,+-5. h/ q0spi@30bb0000 2fsl,imx8mq-qspifsl,imx7d-qspi0}QuadSPIQuadSPI-memory k Lqspi_enqspi Edisabledsdma@30bd00002fsl,imx8mq-sdmafsl,imx7d-sdma0 tLipgahbXcimx/sdma/sdma-imx7d.binethernet@30be00002fsl,imx8mq-fecfsl,imx6sx-fec0$vwx("Lipgahbptpenet_clk_refenet_outEokaydefault12rmii6mdio Eokayswitch@02marvell,mv88e60853default'9ports port@0 gigabit_proc4port@1netaux5port@2cpu6fixed-linkdport@3 netright7port@4netleft8mdio switchphy@094switchphy@195switchphy@29switchphy@397switchphy@498bus@32c000002fsl,imx8mq-aips-bussimple-bus  W22@interrupt-controller@32e2d000$2fsl,imx8m-irqsteerfsl,imx-irqsteer2 Lipg@gpu@38000000 2vivante,gc8  fopLcoreshaderbusreg(Uadop(e|////:usb@381000002fsl,imx8mq-dwc3snps,dwc38Lbus_earlyrefsuspendUneVH|e ( ;;usb2-phyusb3-phy<Eokay3hostusb-phy@381f00402fsl,imx8mq-usb-phy8@@LphyUeH|Eokay;=;usb@382000002fsl,imx8mq-dwc3snps,dwc38 Lbus_earlyrefsuspendUneVH|e ) >>usb2-phyusb3-phy?Eokay3hostusb-phy@382f00402fsl,imx8mq-usb-phy8/@@LphyUeH|Eokay;@>pcie@338000002fsl,imx8mq-pcie3@ }dbiconfig pciG0WQ[ zmsih{}|{zABBBpciephyappsturnoffEokaydefaultC '~}D Lpciepcie_auxpcie_phypcie_buspcie@33c000002fsl,imx8mq-pcie3@' }dbiconfig pci0W' Q[ Jmsih{MLKJAB"B$B%pciephyappsturnoffEokaydefaultE 'F Lpciepcie_auxpcie_phypcie_businterrupt-controller@38800000 2arm,gic-v3(88 1 1 1   ddr-pmu@3d800000%2fsl,imx8mq-ddr-pmufsl,imx8m-ddr-pmu=@ bchosen$/soc@0/bus@30800000/serial@30860000bitbang-mdio2virtual,mdio-gpiodefaultGH' ' ethernet-phy@0 '2clock-pcie0-refclk 2fixed-clockDclock-pcie1-refclk 2fixed-clockFregulator-12p0-main2regulator-fixed 12V_MAINIregulator-5p0-main2regulator-fixedI5V_MAINLK@LK@@regulator-3p3-main2regulator-fixedI 3V3V_MAIN2Z2ZKregulator-vsd-3v3defaultJ2regulator-fixedK3V3_SD2Z2Z /0regulator-armdefaultL2regulator-gpioI0V9_ARM B@ !B@  interrupt-parent#address-cells#size-cellsmodelcompatiblegpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3serial0serial1serial2serial3spi0spi1spi2mdio-gpio0rtc0#clock-cellsclock-frequencyclock-output-namesphandledevice_typeregclock-latencyclocksenable-methodnext-level-cacheoperating-points-v2#cooling-cellsnvmem-cellsnvmem-cell-namescpu-supplyopp-sharedopp-hzopp-microvoltopp-supported-hwclock-latency-nsopp-suspendinterruptsinterrupt-affinitypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicearm,no-tick-in-suspendrangesdma-rangesgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsgpio-rangespinctrl-namespinctrl-0gpio-hoggpiosoutput-lowline-nameoutput-highlittle-endianfsl,tmu-rangefsl,tmu-calibration#thermal-sensor-cellsstatusclock-names#dma-cellsfsl,sdma-ram-script-namefsl,pins#mux-control-cellsmux-reg-masksregmapoffsetlinux,keycodewakeup-source#reset-cells#power-domain-cellspower-domainspower-supply#pwm-cellscurrent-speedzii,eeprom-name#sound-dai-cellsdmasdma-namesassigned-clocksassigned-clock-parentsassigned-clock-rates#phy-cellsinterrupt-namesregulator-min-microvoltregulator-max-microvoltregulator-always-onreset-gpiosfsl,tuning-start-tapfsl,tuning-stepbus-widthpinctrl-1pinctrl-2vqmmc-supplynon-removableno-sdno-sdiocd-gpiosvmmc-supplyreg-namesfsl,num-tx-queuesfsl,num-rx-queuesphy-handlephy-modedsa,membereeprom-lengthlabelethernetfull-duplexfsl,channelfsl,num-irqsphysphy-namesusb3-resume-missing-casdr_modevbus-supplybus-rangenum-lanesnum-viewportinterrupt-map-maskinterrupt-mapfsl,max-link-speedresetsreset-namesreset-gpiostdout-pathregulator-namevin-supplyenable-active-highstates