w8pH(ppine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53arm,armv8xpscicpu@1}cpuarm,cortex-a53arm,armv8xpscicpu@2}cpuarm,cortex-a53arm,armv8xpscicpu@3}cpuarm,cortex-a53arm,armv8xpsci l2-cache0cacheopp_table0operating-points-v2opp-408000000Q~#@4opp-600000000#F~#@opp-8160000000,B@#@opp-1008000000<#@opp-1200000000G(#@opp-1296000000M?d #@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell@G Rapb_pclk^ arm-pmuarm,cortex-a53-pmu0Gdefgi psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0G   xin24m fixed-clock|n6xin24m4i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s G)7Ri2s_clki2s_hclk txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s G*8Ri2s_clki2s_hclk  txrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s G+9Ri2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif G.: Rmclkhclk txdefault  disabledpdm@ff040000 rockchip,pdm=RRpdm_clkpdm_hclk rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd+3io-domains"rockchip,rk3328-io-voltage-domainokay*8power-controller!rockchip,rk3328-power-controllerE+pd_hevc@6pd_video@5pd_vpu@8reboot-modesyscon-reboot-modeY`RBlRBzRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart G7&Rbaudclkapb_pclk  ^default  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart G8'Rbaudclkapb_pclk  ^default  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart G9(Rbaudclkapb_pclk  ^defaultokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c G$+7 Ri2cpclkdefault  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c G%+8 Ri2cpclkdefault!okaypmic@18rockchip,rk805 "G|xin32krk805-clkout2default#$$$$ $regulatorsDCDC_REG1 $vdd_logic3 4K c0xregulator-state-memB@DCDC_REG2$vdd_arm3 4K c0xregulator-state-mem~DCDC_REG3$vcc_ddrxregulator-state-memDCDC_REG4$vcc_io32ZK2Zxregulator-state-mem2ZLDO_REG1$vdd_183w@Kw@xregulator-state-memw@LDO_REG2 $vcc_18emmc3w@Kw@xregulator-state-memw@LDO_REG3$vdd_103B@KB@xregulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c G&+9 Ri2cpclkdefault% disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c G'+: Ri2cpclkdefault& disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi G1+ Rspiclkapb_pclk  txrxdefault'()* disabledwatchdog@ff1a0000 snps,dw-wdt G(pwm@ff1b0000rockchip,rk3328-pwm< Rpwmpclkdefault+ disabledpwm@ff1b0010rockchip,rk3328-pwm< Rpwmpclkdefault, disabledpwm@ff1b0020rockchip,rk3328-pwm < Rpwmpclkdefault- disabledpwm@ff1b0030rockchip,rk3328-pwm0 G2< Rpwmpclkdefault. disabledthermal-zonessoc-thermal/tripstrip-point0#p/passivetrip-point1#L/passive0soc-crit#s/ criticalcooling-mapsmap0:0 ?Ntsadc@ff250000rockchip,rk3328-tsadc% G:[$kP$Rtsadcapb_pclkinitdefaultsleep121B tsadc-apb3okay/adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( GP %Rsaradcapb_pclkV saradc-apb disablediommu@ff330200rockchip,iommu3 G` h265e_mmu+ disablediommu@ff340800rockchip,iommu4@ Gb vepu_mmu+ disablediommu@ff350800rockchip,iommu5@ G vpu_mmu+ disablediommu@ff360480rockchip,iommu 6@6@ GJ rkvdec_mmu+ disablediommu@ff373f00rockchip,iommu7? G vop_mmu+ disabledclock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD3|8[x=&'(ABDC"\5H4$Ez444|kn6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phy4Rphyclk usb480m_phy|[{E5okay5otg-port\$G;<=otg-bvalidotg-idlinestateokayDhost-port\ G> linestateokayEdwmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ G  =!JNRbiuciuciu-driveciu-samplegrрokaydefault6789:dwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ G  >"KORbiuciuciu-driveciu-samplegrр disableddwmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ G ?#LPRbiuciuciu-driveciu-samplegrрokaydefault ;<=ethernet@ff540000rockchip,rk3328-gmacT Gmacirq8dWXZYMRstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth3okay[dfE>>inputdrgmiidefault?  %@5 K'P`$iethernet@ff550000rockchip,rk3328-gmacU3 Gmacirq8TSSUVIRstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphybdstmmacethmac-phyrmiirA disabledmdiosnps,dwmac-mdio+phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultBC}Ausb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X GMRotghost@ D usb2-phyokayusb@ff5c0000 generic-ehci\ G N5 RusbhostutmiEusbokayusb@ff5d0000 generic-ohci] G N5 RusbhostutmiEusbokayinterrupt-controller@ff811000 arm,gic-400@ @ `  G pinctrlrockchip,rk3328-pinctrl3+@gpio0@ff210000rockchip,gpio-bank! G3Qgpio1@ff220000rockchip,gpio-bank" G4@gpio2@ff230000rockchip,gpio-bank# G5"gpio3@ff240000rockchip,gpio-bank$ G6pcfg-pull-up"Hpcfg-pull-down/Ppcfg-pull-none>Fpcfg-pull-none-2ma>KOpcfg-pull-up-2ma"Kpcfg-pull-up-4ma"KIpcfg-pull-none-4ma>KLpcfg-pull-down-4ma/Kpcfg-pull-none-8ma>KJpcfg-pull-up-8ma"KKpcfg-pull-none-12ma>K Mpcfg-pull-up-12ma"K Npcfg-output-highZpcfg-output-lowfpcfg-input-high"qGpcfg-inputqi2c0i2c0-xfer ~FF i2c1i2c1-xfer ~FF!i2c2i2c2-xfer ~ FF%i2c3i2c3-xfer ~FF&i2c3-gpio ~FFhdmi_i2chdmii2c-xfer ~FFpdm-0pdmm0-clk~F pdmm0-fsync~Fpdmm0-sdi0~F pdmm0-sdi1~Fpdmm0-sdi2~Fpdmm0-sdi3~Fpdmm0-clk-sleep~Gpdmm0-sdi0-sleep~Gpdmm0-sdi1-sleep~Gpdmm0-sdi2-sleep~Gpdmm0-sdi3-sleep~Gpdmm0-fsync-sleep~Gtsadcotp-gpio~ F1otp-out~ F2uart0uart0-xfer ~ FHuart0-cts~ Fuart0-rts~ Fuart0-rts-gpio~ Fuart1uart1-xfer ~FHuart1-cts~Fuart1-rts~Fuart1-rts-gpio~Fuart2-0uart2m0-xfer ~FHuart2-1uart2m1-xfer ~FHspi0-0spi0m0-clk~Hspi0m0-cs0~ Hspi0m0-tx~ Hspi0m0-rx~ Hspi0m0-cs1~ Hspi0-1spi0m1-clk~Hspi0m1-cs0~Hspi0m1-tx~Hspi0m1-rx~Hspi0m1-cs1~Hspi0-2spi0m2-clk~H'spi0m2-cs0~H*spi0m2-tx~H(spi0m2-rx~H)i2s1i2s1-mclk~Fi2s1-sclk~Fi2s1-lrckrx~Fi2s1-lrcktx~Fi2s1-sdi~Fi2s1-sdo~Fi2s1-sdio1~Fi2s1-sdio2~Fi2s1-sdio3~Fi2s1-sleep~GGGGGGGGGi2s2-0i2s2m0-mclk~Fi2s2m0-sclk~Fi2s2m0-lrckrx~Fi2s2m0-lrcktx~Fi2s2m0-sdi~Fi2s2m0-sdo~Fi2s2m0-sleep`~GGGGGGi2s2-1i2s2m1-mclk~Fi2s2m1-sclk~Fi2sm1-lrckrx~Fi2s2m1-lrcktx~Fi2s2m1-sdi~Fi2s2m1-sdo~Fi2s2m1-sleepP~GGGGGspdif-0spdifm0-tx~Fspdif-1spdifm1-tx~Fspdif-2spdifm2-tx~F sdmmc0-0sdmmc0m0-pwren~Isdmmc0m0-gpio~Isdmmc0-1sdmmc0m1-pwren~Isdmmc0m1-gpio~IRsdmmc0sdmmc0-clk~J6sdmmc0-cmd~K7sdmmc0-dectn~I8sdmmc0-wrprt~Isdmmc0-bus1~Ksdmmc0-bus4@~KKKK9sdmmc0-gpio~IIIIIIIIsdmmc0extsdmmc0ext-clk~Lsdmmc0ext-cmd~Isdmmc0ext-wrprt~Isdmmc0ext-dectn~Isdmmc0ext-bus1~Isdmmc0ext-bus4@~IIIIsdmmc0ext-gpio~IIIIIIIIsdmmc1sdmmc1-clk~ Jsdmmc1-cmd~ Ksdmmc1-pwren~Ksdmmc1-wrprt~Ksdmmc1-dectn~Ksdmmc1-bus1~Ksdmmc1-bus4@~KKKKsdmmc1-gpio~ I IIIIIIIIemmcemmc-clk~M;emmc-cmd~N<emmc-pwren~Femmc-rstnout~Femmc-bus1~Nemmc-bus4@~NNNNemmc-bus8~NNNNNNNN=pwm0pwm0-pin~F+pwm1pwm1-pin~F,pwm2pwm2-pin~F-pwmirpwmir-pin~F.gmac-1rgmiim1-pins`~ J LLJLLL L LJ JLLJJJ JLJJJJ?rmiim1-pins~OMOOOO O OM M F FFFFFgmac2phyfephyled-speed100~Ffephyled-speed10~Ffephyled-duplex~Ffephyled-rxm0~Ffephyled-txm0~Ffephyled-linkm0~Ffephyled-rxm1~FBfephyled-txm1~Ffephyled-linkm1~FCtsadc_pintsadc-int~ Ftsadc-gpio~ Fhdmi_pinhdmi-cec~Fhdmi-hpd~Pcif-0dvp-d2d9-m0~FFFFF F F FFFFFcif-1dvp-d2d9-m1~FFFFFFFFFFFFpmicpmic-int-l~H#usb2usb20-host-drv~FTusb3usb30-host-drv~FSchosenserial2:1500000n8external-gmac-clock fixed-clocksY@ gmac_clkin|>sdmmc-regulatorregulator-fixed 0QdefaultR$vcc_sd32ZK2Z:vcc-host-5v-regulatorregulator-fixed 0QdefaultS $vcc_host_5vx$vcc-host1-5v-regulatorregulator-fixed 0QdefaultT $vcc_host1_5vx$vcc-sysregulator-fixed$vcc_sysx3LK@KLK@$ compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellsdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsclock-names#dma-cellsinterrupt-affinity#clock-cellsclock-frequencyclock-output-namesdmasdma-namesstatuspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supply#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsinterrupt-names#iommu-cells#reset-cellsassigned-clock-parents#phy-cellsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplynon-removablevqmmc-supplyclock_in_outmax-speedphy-supplyphy-modesnps,force_thresh_dma_modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-names#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplyenable-active-high