8 ,(l )Qualcomm Technologies, Inc. IPQ8074-HK01qcom,ipq8074-hk01qcom,ipq8074 ,soc = simple-buspinctrl@1000000qcom,ipq8074-pinctrlD0 HScoserial4_pinmuxmuxgpio23gpio24 blsp4_uart1interrupt-controller@b000000qcom,msm-qgic2oD  timerarm,armv8-timer0Htimer@b120000 =arm,armv7-timer-memD $frame@b120000HD   frame@b123000 H D 0 disabledframe@b124000 H D @ disabledframe@b125000 H D P disabledframe@b126000 H D ` disabledframe@b127000 H D p disabledframe@b128000 HD  disabledgcc@1800000qcom,gcc-ipq8074Dserial@78b3000%qcom,msm-uartdm-v1.4qcom,msm-uartdmD0 H4& coreifaceok defaultcpus cpu@0!cpuarm,cortex-a53arm,armv8D->pscicpu@1!cpuarm,cortex-a53arm,armv8>psciD-cpu@2!cpuarm,cortex-a53arm,armv8>psciD-cpu@3!cpuarm,cortex-a53arm,armv8>psciD-l2-cachecacheLpsci arm,psci-1.0Esmcpmuarm,armv8-pmuv3 Hclockssleep_clk fixed-clock}xo fixed-clock$aliasesX/soc/serial@78b3000chosen`serial0memory!memoryD@  modelcompatible#address-cells#size-cellsinterrupt-parentrangesreginterruptsgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsphandlepinsfunctionbias-disableclock-frequencyframe-numberstatus#clock-cells#reset-cellsclocksclock-namespinctrl-0pinctrl-namesdevice_typenext-level-cacheenable-methodcache-levelserial0stdout-path