8|( 'D,rockchip,rk3288-evb-act8846rockchip,rk3288&7Rockchip RK3288 EVB ACT8846aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]@krr cpu@501#cpuarm,cortex-a12/3:N]@krrcpu@502#cpuarm,cortex-a12/3:N]@krrcpu@503#cpuarm,cortex-a12/3:N]@krropp-table-0operating-points-v2opp-126000000 opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ka  2pclktimerdisplay-subsystemrockchip,display-subsystem> mmc@ff0c0000rockchip,rk3288-dw-mshcDр kDrv2biuciuciu-driveciu-sampleR / @3]resetiokaypzdefault mmc@ff0d0000rockchip,rk3288-dw-mshcDр kEsw2biuciuciu-driveciu-sampleR !/ @3]reset idisabledmmc@ff0e0000rockchip,rk3288-dw-mshcDр kFtx2biuciuciu-driveciu-sampleR "/@3]reset idisabledmmc@ff0f0000rockchip,rk3288-dw-mshcDр kGuy2biuciuciu-driveciu-sampleR #/@3]resetiokaypzdefaultsaradc@ff100000rockchip,saradc/ $kI[2saradcapb_pclk3W ]saradc-apbiokay zspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR2spiclkapb_pclk  txrx ,default/ idisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS2spiclkapb_pclk txrx -default / idisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT2spiclkapb_pclktxrx .default!"#$/ idisabledi2c@ff140000rockchip,rk3288-i2c/ >2i2ckMdefault% idisabledi2c@ff150000rockchip,rk3288-i2c/ ?2i2ckOdefault& idisabledi2c@ff160000rockchip,rk3288-i2c/ @2i2ckPdefault' idisabledi2c@ff170000rockchip,rk3288-i2c/ A2i2ckQdefault(iokaymserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 7&0kMU2baudclkapb_pclktxrxdefault)iokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 8&0kNV2baudclkapb_pclktxrxdefault*iokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 9&0kOW2baudclkapb_pclkdefault+iokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :&0kPX2baudclkapb_pclktxrxdefault,iokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;&0kQY2baudclkapb_pclk  txrxdefault-iokaydma-controller@ff250000arm,pl330arm,primecell/%@=Hck 2apb_pclkthermal-zonesreserve-thermalz.cpu-thermalzd.tripscpu_alert0p*passive/cpu_alert1$*passive0cpu_crit_ *criticalcooling-mapsmap0/0map100gpu-thermalzd.tripsgpu_alert0p*passive1gpu_crit_ *criticalcooling-mapsmap01 2tsadc@ff280000rockchip,rk3288-tsadc/( %kHZ2tsadcapb_pclk3 ]tsadc-apbinitdefaultsleep3435siokay'>.ethernet@ff290000rockchip,rk3288-gmac/)Ymacirqeth_wake_irq58kfgc]M2stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B ]stmmacethiokayi6trgmii}input 7 'B@8default90usb@ff500000 generic-ehci/P k:usbiokayusb@ff520000 generic-ohci/R )k:usb idisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T k2otg host; usb2-phyiokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X k2otg otg,>M@@ < usb2-phy idisabledusb@ff5c0000 generic-ehci/\ k idisableddma-controller@ff600000arm,pl330arm,primecell/`@=Hck 2apb_pclk idisabledi2c@ff650000rockchip,rk3288-i2c/e <2i2ckLdefault=iokaysyr827@40silergy,syr827\/@yvdd_cpu Pp> syr828@41silergy,syr828\/Ayvdd_gpu Pp>rrtc@51haoyu,hym8563/Q&?default@xin32kact8846@5aactive-semi,act8846/Ziokay>>> >A!>-BregulatorsREG1yVCC_DDROOREG2yVCC_IO2Z2ZAREG3yVDD_LOG ``REG4yVCC_20BREG5 yVCCIO_SDw@2ZREG6 yVDD10_LCDB@B@REG7 yVCCA_CODEC2Z2ZREG8yVCCA_TP2Z2ZREG9 yVCCIO_PMU2Z2ZREG10yVDD_10B@B@REG11yVCC_18w@w@REG12 yVCC18_LCDw@w@i2c@ff660000rockchip,rk3288-i2c/f =2i2ckNdefaultC idisabledpwm@ff680000rockchip,rk3288-pwm/h9defaultDk_iokay}pwm@ff680010rockchip,rk3288-pwm/h9defaultEk_ idisabledpwm@ff680020rockchip,rk3288-pwm/h 9defaultFk_ idisabledpwm@ff680030rockchip,rk3288-pwm/h09defaultGk_ idisabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/spower-controller!rockchip,rk3288-power-controllerDh Ypower-domain@9/ kchgfdehilkj$XHIJKLMNOPDpower-domain@11/ kopXQRDpower-domain@12/ kXSDpower-domain@13/ kXTUDreboot-modesyscon-reboot-mode_fRBrRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/vk 2xin24m5Hjk$#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w5edp-phyrockchip,rk3288-dp-phykh224miokayiio-domains"rockchip,rk3288-io-voltage-domain idisabledusbphyrockchip,rk3288-usb-phyiokayusb-phy@320/ k]2phyclk3 ]phy-reset<usb-phy@334/4k^2phyclk3 ]phy-reset:usb-phy@348/Hk_2phyclk3 ]phy-reset;watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/kp Oiokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/kT 2mclkhclkVtx 6defaultW5 idisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ 5kR2i2s_clki2s_hclkVVtxrxdefaultX idisabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 k}2aclkhclksclkapb_pclk3 ]crypto-rstiommu@ff900800rockchip,iommu/@ k 2aclkiface idisablediommu@ff914000rockchip,iommu /@P k 2aclkiface idisabledrga@ff920000rockchip,rk3288-rga/ kj2aclkhclksclk7Y 3ilm ]coreaxiahbvop@ff930000rockchip,rk3288-vop / k2aclk_vopdclk_vophclk_vop7Y 3def ]axiahbdclkEZiokayport endpoint@0/L[nendpoint@1/L\jendpoint@2/L]dendpoint@3/L^giommu@ff930300rockchip,iommu/ k 2aclkiface7Y iokayZvop@ff940000rockchip,rk3288-vop / k2aclk_vopdclk_vophclk_vop7Y 3 ]axiahbdclkE_iokayport endpoint@0/L`oendpoint@1/Lakendpoint@2/Lbeendpoint@3/Lchiommu@ff940300rockchip,iommu/ k 2aclkiface7Y iokay_dsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ k~d 2refpclk7Y 5 idisabledportsport@0/endpoint@0/Ld]endpoint@1/Lebport@1/lvds@ff96c000rockchip,rk3288-lvds/@kg 2pclk_lvdslcdcf7Y 5 idisabledportsport@0/endpoint@0/Lg^endpoint@1/Lhcport@1/dp@ff970000rockchip,rk3288-dp/@ bkic2dppclkidp7Y 3o]dp5iokay\portsport@0/endpoint@0/Lj\endpoint@1/Lkaport@1/endpoint@0/Llhdmi@ff980000rockchip,rk3288-dw-hdmi/0 gkhmn2iahbisfrcec7Y 5iokayfmportsport@0/endpoint@0/Ln[endpoint@1/Lo`port@1/video-codec@ff9a0000rockchip,rk3288-vpu/   Yvepuvdpuk 2aclkhclkEp7Y iommu@ff9a0800rockchip,iommu/ k 2aclkiface7Y piommu@ff9c0440rockchip,iommu /@@@ ok 2aclkiface idisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/$ Yjobmmugpuk:qN7Y iokayrr2opp-table-1operating-points-v2qopp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon/ Tqos@ffaa0080rockchip,rk3288-qossyscon/ Uqos@ffad0000rockchip,rk3288-qossyscon/ Iqos@ffad0100rockchip,rk3288-qossyscon/ Jqos@ffad0180rockchip,rk3288-qossyscon/ Kqos@ffad0400rockchip,rk3288-qossyscon/ Lqos@ffad0480rockchip,rk3288-qossyscon/ Mqos@ffad0500rockchip,rk3288-qossyscon/ Hqos@ffad0800rockchip,rk3288-qossyscon/ Nqos@ffad0880rockchip,rk3288-qossyscon/ Oqos@ffad0900rockchip,rk3288-qossyscon/ Pqos@ffae0000rockchip,rk3288-qossyscon/ Sqos@ffaf0000rockchip,rk3288-qossyscon/ Qqos@ffaf0080rockchip,rk3288-qossyscon/ Rdma-controller@ffb20000arm,pl330arm,primecell/@=Hck 2apb_pclkVefuse@ffb40000rockchip,rk3288-efuse/ kq 2pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400~@/ @ `   pinctrlrockchip,rk3288-pinctrl5gpio@ff750000rockchip,gpio-bank/u Qk@~?gpio@ff780000rockchip,gpio-bank/x RkA~gpio@ff790000rockchip,gpio-bank/y SkB~gpio@ff7a0000rockchip,gpio-bank/z TkC~gpio@ff7b0000rockchip,gpio-bank/{ UkD~7gpio@ff7c0000rockchip,gpio-bank/| VkE~gpio@ff7d0000rockchip,gpio-bank/} WkF~gpio@ff7e0000rockchip,gpio-bank/~ XkG~{gpio@ff7f0000rockchip,gpio-bank/ YkH~hdmihdmi-cec-c0shdmi-cec-c7shdmi-ddc sshdmi-ddc-unwedge tspcfg-output-lowtpcfg-pull-upupcfg-pull-downvpcfg-pull-nonespcfg-pull-none-12ma ysuspendglobal-pwroffsddrio-pwroffsddr0-retentionuddr1-retentionuedpedp-hpd vi2c0i2c0-xfer ss=i2c1i2c1-xfer ss%i2c2i2c2-xfer  s sCi2c3i2c3-xfer ss&i2c4i2c4-xfer ss'i2c5i2c5-xfer ss(i2s0i2s0-bus`ssssssXlcdclcdc-ctl@ssssfsdmmcsdmmc-clkw sdmmc-cmdxsdmmc-cdusdmmc-bus1usdmmc-bus4@xxxxsdmmc-pwr ssdio0sdio0-bus1usdio0-bus4@uuuusdio0-cmdusdio0-clkssdio0-cdusdio0-wpusdio0-pwrusdio0-bkpwrusdio0-intusdio1sdio1-bus1usdio1-bus4@uuuusdio1-cdusdio1-wpusdio1-bkpwrusdio1-intusdio1-cmdusdio1-clkssdio1-pwr uemmcemmc-clksemmc-cmduemmc-pwr uemmc-bus1uemmc-bus4@uuuuemmc-bus8uuuuuuuuspi0spi0-clk uspi0-cs0 uspi0-txuspi0-rxuspi0-cs1uspi1spi1-clk uspi1-cs0 u spi1-rxuspi1-txuspi2spi2-cs1uspi2-clku!spi2-cs0u$spi2-rxu#spi2-tx u"uart0uart0-xfer us)uart0-ctsuuart0-rtssuart1uart1-xfer u s*uart1-cts uuart1-rts suart2uart2-xfer us+uart3uart3-xfer us,uart3-cts uuart3-rts suart4uart4-xfer us-uart4-cts uuart4-rts stsadcotp-pin s3otp-out s4pwm0pwm0-pinsDpwm1pwm1-pinsEpwm2pwm2-pinsFpwm3pwm3-pinsGgmacrgmii-pinsssssyyyysss yyss9rmii-pinsssssssssssspdifspdif-tx sWpcfg-pull-none-drv-8mawpcfg-pull-up-drv-8maxbacklightbl-ens|buttonspwrbtnulcdlcd-csslcd-enspmicpmic-intu@usbhost-vbus-drvseth_phyeth-phy-pwrswifiwifi-pwr smemory@0#memory/adc-keys adc-keyszbuttons.w@button-up HVolume UpNsYbutton-down HVolume DownNrYbutton-menuHMenuNY button-escHEscNYB@button-homeHHomeNfY backlightpwm-backlights  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ {default|}B@~external-gmac-clock fixed-clocksY@ ext_gmac8panellg,lp079qx1-sp0v~ {portsportendpointLlgpio-keys gpio-keysdefaultkey-power ?NtHGPIO Key Powerdvcc-host-regulatorregulator-fixed  ?default yvcc_hostvcc-phy-regulatorregulator-fixed  ?defaultyvcc_phy2Z2Z6vsys-regulatorregulator-fixedyvcc_sysLK@LK@>sdmmc-regulatorregulator-fixed { defaultyvcc_sd2Z2Z Avcc-lcdregulator-fixed  {defaultyvcc_lcdAvcc-wlregulator-fixed  { defaultyvcc_wl #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplyvp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltbrightness-levelsdefault-brightness-levelenable-gpiospwmsbacklightpower-supplyautorepeatlinux,input-typewakeup-sourcedebounce-intervalenable-active-highstartup-delay-us