8d( ,google,veyron-fievel-rev8google,veyron-fievel-rev7google,veyron-fievel-rev6google,veyron-fievel-rev5google,veyron-fievel-rev4google,veyron-fievel-rev3google,veyron-fievel-rev2google,veyron-fievel-rev1google,veyron-fievel-rev0google,veyron-fievelgoogle,veyronrockchip,rk3288&7Google Fievelaliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0f0000arm-pmuarm,cortex-a12-pmu0cpus rockchip,rk3066-smpcpu@500(cpuarm,cortex-a1248?Sb@pwr cpu@501(cpuarm,cortex-a1248?Sb@pwrcpu@502(cpuarm,cortex-a1248?Sb@pwrcpu@503(cpuarm,cortex-a1248?Sb@pwropp-table-0operating-points-v2opp-126000000 opp-216000000  opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJopp-1608000000_" opp-1704000000epopp-1800000000kI\reserved-memorydma-unusable@fe0000004oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6 timer@ff810000rockchip,rk3288-timer4  H pa  7pclktimerdisplay-subsystemrockchip,display-subsystemC mmc@ff0c0000rockchip,rk3288-dw-mshcIр pDrv7biuciuciu-driveciu-sampleW 4 @8breset ndisabledmmc@ff0d0000rockchip,rk3288-dw-mshcIр pEsw7biuciuciu-driveciu-sampleW !4 @8bresetnokayu default  %btmrvl@2marvell,sd8897-bt4&2 defaultmmc@ff0e0000rockchip,rk3288-dw-mshcIр pFtx7biuciuciu-driveciu-sampleW "4@8breset ndisabledmmc@ff0f0000rockchip,rk3288-dw-mshcIр pGuy7biuciuciu-driveciu-sampleW #4@8bresetnokayuEWudefault saradc@ff100000rockchip,saradc4 $pI[7saradcapb_pclk8W bsaradc-apb ndisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spipAR7spiclkapb_pclk  txrx ,default4 ndisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spipBS7spiclkapb_pclk txrx -default !4 ndisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spipCT7spiclkapb_pclktxrx .default"#$%4nokay flash@0jedec,spi-nor4i2c@ff140000rockchip,rk3288-i2c4 >7i2cpMdefault&nokay2dtpm@20infineon,slb9645tt4 i2c@ff150000rockchip,rk3288-i2c4 ?7i2cpOdefault' ndisabledi2c@ff160000rockchip,rk3288-i2c4 @7i2cpPdefault(nokay2,ts3a227e@3b ti,ts3a227e4;&)default*i2c@ff170000rockchip,rk3288-i2c4 A7i2cpQdefault+ ndisabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart4 7'1pMU7baudclkapb_pclktxrxdefault ,-.nokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart4 8'1pNV7baudclkapb_pclktxrxdefault/nokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart4i 9'1pOW7baudclkapb_pclkdefault0nokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart4 :'1pPX7baudclkapb_pclktxrxdefault1 ndisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart4 ;'1pQY7baudclkapb_pclk  txrxdefault2 ndisableddma-controller@ff250000arm,pl330arm,primecell4%@>Idp 7apb_pclkthermal-zonesreserve-thermal{3cpu-thermal{d3tripscpu_alert0p/passive4cpu_alert1$/passive5cpu_crit /criticalcooling-mapsmap040map150gpu-thermal{d3tripsgpu_alert04/passive6gpu_crit /criticalcooling-mapsmap06 7tsadc@ff280000rockchip,rk3288-tsadc4( %pHZ7tsadcapb_pclk8 btsadc-apbinitdefaultsleep898:Hnokay(?3ethernet@ff290000rockchip,rk3288-gmac4)Zmacirqeth_wake_irq:8pfgc]M7stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8B bstmmacethnokayjz;input<rgmii=default>?@A0  'u0 mdio0snps,dwmac-mdioethernet-phy@14<usb@ff500000 generic-ehci4P pBusbnokay'usb@ff520000 generic-ohci4R )pBusb ndisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc24T p7otg=hostC usb2-phyEnokay\usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc24X p7otg=hosts@@ D usb2-phynokayjzzD\usb@ff5c0000 generic-ehci4\ p ndisableddma-controller@ff600000arm,pl330arm,primecell4`@>Idp 7apb_pclk ndisabledi2c@ff650000rockchip,rk3288-i2c4e <7i2cpLdefaultEnokay2dpmic@1brockchip,rk8084xin32kwifibt_32kin&)default FGH  %I2?J JIKregulatorsDCDC_REG1Vvdd_armey q q regulator-state-memDCDC_REG2Vvdd_gpuey 5qregulator-state-memDCDC_REG3 Vvcc135_ddreyregulator-state-memDCDC_REG4Vvcc_18eyw@w@regulator-state-memw@LDO_REG3Vvdd_10eyB@B@regulator-state-memB@LDO_REG7 Vvdd10_lcdeyB@B@regulator-state-memSWITCH_REG1 Vvcc33_lcdeyaregulator-state-memLDO_REG6 Vvcc18_codeceyw@w@bregulator-state-memLDO_REG2eyw@w@ Vvdd18_lcdtregulator-state-memLDO_REG8ey2Z2Z Vvcc33_ccdregulator-state-memSWITCH_REG2 Vvcc33_lan=i2c@ff660000rockchip,rk3288-i2c4f =7i2cpNdefaultLnokay2 max98090@10maxim,max980904&M7mclkpqdefaultNpwm@ff680000rockchip,rk3288-pwm4hdefaultOp_ ndisabledpwm@ff680010rockchip,rk3288-pwm4hdefaultPp_nokaypwm@ff680020rockchip,rk3288-pwm4h defaultQp_ ndisabledpwm@ff680030rockchip,rk3288-pwm4h0defaultRp_ ndisabledsram@ff700000 mmio-sram4ppsmp-sram@0rockchip,rk3066-smp-sram4sram@ff720000#rockchip,rk3288-pmu-srammmio-sram4rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd4spower-controller!rockchip,rk3288-power-controller(jhz fpower-domain@94 pchgfdehilkj$<STUVWXYZ[(power-domain@114 pop<\](power-domain@124 p<^(power-domain@134 p<_`(reboot-modesyscon-reboot-modeCJRBVRBdRB tRBsyscon@ff740000rockchip,rk3288-sgrfsyscon4tclock-controller@ff760000rockchip,rk3288-cru4vp 7xin24m:Hjjk$#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd4w:edp-phyrockchip,rk3288-dp-phyph724m ndisabledvio-domains"rockchip,rk3288-io-voltage-domainnokayIIIa busbphyrockchip,rk3288-usb-phynokayusb-phy@3204 p]7phyclk8 bphy-resetDusb-phy@33444p^7phyclk8 bphy-resetBusb-phy@3484Hp_7phyclk8 bphy-resetCwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt4pp Onokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif4 pT 7mclkhclkctx 6defaultd: ndisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s4  5pR7i2s_clki2s_hclkcctxrxdefaulte $ ?nokaycrypto@ff8a0000rockchip,rk3288-crypto4@ 0 p}7aclkhclksclkapb_pclk8 bcrypto-rstiommu@ff900800rockchip,iommu4@ p 7aclkiface Y ndisablediommu@ff914000rockchip,iommu 4@P p 7aclkiface Y f ndisabledrga@ff920000rockchip,rk3288-rga4 pj7aclkhclksclk f 8ilm bcoreaxiahbvop@ff930000rockchip,rk3288-vop 4 p7aclk_vopdclk_vophclk_vop f 8def baxiahbdclk gnokayport endpoint@04 h{endpoint@14 iwendpoint@24 jqendpoint@34 ktiommu@ff930300rockchip,iommu4 p 7aclkiface f  Ynokaygvop@ff940000rockchip,rk3288-vop 4 p7aclk_vopdclk_vophclk_vop f 8 baxiahbdclk l ndisabledport endpoint@04 m|endpoint@14 nxendpoint@24 orendpoint@34 puiommu@ff940300rockchip,iommu4 p 7aclkiface f  Y ndisabledldsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi4@ p~d 7refpclk f : ndisabledportsport@04endpoint@04 qjendpoint@14 roport@14lvds@ff96c000rockchip,rk3288-lvds4@pg 7pclk_lvdslcdcs f : ndisabledportsport@04endpoint@04 tkendpoint@14 upport@14dp@ff970000rockchip,rk3288-dp4@ bpic7dppclkvdp f 8obdp: ndisabledportsport@04endpoint@04 wiendpoint@14 xnport@14hdmi@ff980000rockchip,rk3288-dw-hdmi41 gphmn7iahbisfrcec f : nokaydefaultunwedgeyzportsport@04endpoint@04 {hendpoint@14 |mport@14video-codec@ff9a0000rockchip,rk3288-vpu4   Zvepuvdpup 7aclkhclk } f iommu@ff9a0800rockchip,iommu4 p 7aclkiface Y f }iommu@ff9c0440rockchip,iommu 4@@@ op 7aclkiface Y ndisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t7604$ Zjobmmugpup?~S f nokay 7opp-table-1operating-points-v2~opp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon4 _qos@ffaa0080rockchip,rk3288-qossyscon4 `qos@ffad0000rockchip,rk3288-qossyscon4 Tqos@ffad0100rockchip,rk3288-qossyscon4 Uqos@ffad0180rockchip,rk3288-qossyscon4 Vqos@ffad0400rockchip,rk3288-qossyscon4 Wqos@ffad0480rockchip,rk3288-qossyscon4 Xqos@ffad0500rockchip,rk3288-qossyscon4 Sqos@ffad0800rockchip,rk3288-qossyscon4 Yqos@ffad0880rockchip,rk3288-qossyscon4 Zqos@ffad0900rockchip,rk3288-qossyscon4 [qos@ffae0000rockchip,rk3288-qossyscon4 ^qos@ffaf0000rockchip,rk3288-qossyscon4 \qos@ffaf0080rockchip,rk3288-qossyscon4 ]dma-controller@ffb20000arm,pl330arm,primecell4@>Idp 7apb_pclkcefuse@ffb40000rockchip,rk3288-efuse4 pq 7pclk_efusecpu-id@74cpu_leakage@174interrupt-controller@ffc01000 arm,gic-400  @4 @ `   pinctrlrockchip,rk3288-pinctrl:defaultsleepgpio@ff750000rockchip,gpio-bank4u Qp@     PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LHUB_USB1_nFALUTPHY_PMEBPHY_INTRECOVERY_SW_LOTP_OUTUSB_OTG_POWER_ENAP_WARM_RESET_HUSB_OTG_nFALUTI2C0_SDA_PMICI2C0_SCL_PMICDEVMODE_LUSB_INT)gpio@ff780000rockchip,gpio-bank4x RpA    gpio@ff790000rockchip,gpio-bank4y SpB    i CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TPgpio@ff7a0000rockchip,gpio-bank4z TpC     FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7VCC5V_GOOD_HFLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOPHY_TXD2PHY_TXD3MAC_RXD2MAC_RXD3PHY_TXD0PHY_TXD1MAC_RXD0MAC_RXD1gpio@ff7b0000rockchip,gpio-bank4{ UpD     MAC_MDCMAC_RXDVMAC_RXERMAC_CLKPHY_TXENMAC_MDIOMAC_RXCLKPHY_RSTPHY_TXCLKUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEgpio@ff7c0000rockchip,gpio-bank4| VpE     USB_OTG_CTL1HUB_USB2_CTL1HUB_USB2_PWR_ENHUB_USB_ILIM_SELUSB_OTG_STATUS_LHUB_USB1_CTL1HUB_USB1_PWR_ENVCC50_HDMI_ENgpio@ff7d0000rockchip,gpio-bank4} WpF     I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETHUB_USB2_nFALUTUSB_OTG_ILIM_SELMgpio@ff7e0000rockchip,gpio-bank4~ XpG     LCD_BL_PWMPWM_LOGBL_ENPWR_LED1TPM_INT_HSPK_ONAP_FLASH_WP_LCPU_NMIDVSOKEDP_HPDDVS1LCD_ENDVS2HDMI_CECI2C4_SDAI2C4_SCLI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDJgpio@ff7f0000rockchip,gpio-bank4 YpH    ^ RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc yhdmi-ddc-unwedge zvcc50-hdmi-en pcfg-output-low pcfg-pull-up pcfg-pull-down *pcfg-pull-none 9pcfg-pull-none-12ma 9 F suspendglobal-pwroff ddrio-pwroff ddr0-retention ddr1-retention edpedp-hpd  i2c0i2c0-xfer Ei2c1i2c1-xfer &i2c2i2c2-xfer   Li2c3i2c3-xfer 'i2c4i2c4-xfer (i2c5i2c5-xfer +i2s0i2s0-bus` elcdclcdc-ctl@ ssdmmcsdmmc-clk sdmmc-cmd sdmmc-cd sdmmc-bus1 sdmmc-bus4@ sdio0sdio0-bus1 sdio0-bus4@ sdio0-cmd sdio0-clk sdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h bt-enable-l bt-host-wake bt-host-wake-l bt-dev-wake-sleep bt-dev-wake-awake bt-dev-wake sdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk emmc-cmd emmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 emmc-reset  spi0spi0-clk  spi0-cs0  spi0-tx spi0-rx spi0-cs1 spi1spi1-clk  spi1-cs0  !spi1-rx  spi1-tx spi2spi2-cs1 spi2-clk "spi2-cs0 %spi2-rx $spi2-tx  #uart0uart0-xfer ,uart0-cts -uart0-rts .uart1uart1-xfer  /uart1-cts  uart1-rts  uart2uart2-xfer 0uart3uart3-xfer 1uart3-cts  uart3-rts  uart4uart4-xfer 2uart4-cts  uart4-rts  tsadcotp-pin  8otp-out  9pwm0pwm0-pin Opwm1pwm1-pin Ppwm2pwm2-pin Qpwm3pwm3-pin Rgmacrgmii-pins  >rmii-pins phy-rst ?phy-pmeb @phy-int Aspdifspdif-tx  dpcfg-pull-none-drv-8ma 9 Fpcfg-pull-up-drv-8ma  Fpcfg-output-high Ubuttonspwr-key-l pmicpmic-int-l Fdvs-1  Gdvs-2 Hrebootap-warm-reset-h  recovery-switchrec-mode-l  tpmtpm-int-h write-protectfw-wp-ap codechp-det int-codec Nmic-det  headsetts3a227e-int-l *buck-5vdrv-5v ledspwr-led1-on pwr-led1-blink usb-bc12usb-otg-ilim-sel usb-usb-ilim-sel usb-hosthub_usb1_pwr_en hub_usb2_pwr_en usb_otg_pwr_en  chosen aserial2:115200n8memory(memory4power-button gpio-keysdefaultkey-power mPower C) st ~d gpio-restart gpio-restart C) default emmc-pwrseqmmc-pwrseq-emmcdefault sdio-pwrseqmmc-pwrseq-simplep 7ext_clockdefault  vcc-5vregulator-fixedVvcc_5veyLK@LK@  JdefaultKvcc33-sysregulator-fixed Vvcc33_sysey2Z2Zvcc50-hdmiregulator-fixed Vvcc50_hdmiey K  defaultvdd-logicpwm-regulator Vvdd_logic   { ey~psound!rockchip,rockchip-audio-max98090default VEYRON-I2S  ! 6M LM  c zvccsysregulator-fixedVvccsysyevcc33-ioregulator-fixedey Vvcc33_ioIvcc5-host1-regulatorregulator-fixed  default Vvcc5_host1eyvcc5-host2-regulatorregulator-fixed  default Vvcc5_host2eyvcc5v-otg-regulatorregulator-fixed  ) default Vvcc5_otgeyexternal-gmac-clock fixed-clocksY@ ext_gmac; #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymarvell,wakeup-pincap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-modephy-supplyrx_delaytx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-uswakeup-sourcephysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosenable-active-highvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codec