;8( ,Freescale i.MX8DXL EVK2fsl,imx8dxl-evkfsl,imx8dxlaliases =/bus@5b000000/ethernet@5b040000 G/bus@5b000000/ethernet@5b050000Q/bus@5d000000/gpio@5d080000W/bus@5d000000/gpio@5d090000]/bus@5d000000/gpio@5d0a0000c/bus@5d000000/gpio@5d0b0000i/bus@5d000000/gpio@5d0c0000o/bus@5d000000/gpio@5d0d0000u/bus@5d000000/gpio@5d0e0000{/bus@5d000000/gpio@5d0f0000/bus@5d000000/mailbox@5d1c0000/bus@5a000000/i2c@5a820000/bus@5b000000/mmc@5b010000/bus@5b000000/mmc@5b020000/bus@5a000000/serial@5a060000cpus cpu@0cpu2arm,cortex-a35psci  cpu@1cpu2arm,cortex-a35psci  l2-cache02cache opp-table2operating-points-v2opp-900000000"5)B@7Iopp-1200000000"G)7IHinterrupt-controller@51a00000 2arm,gic-v3 QQ Te z reserved-memory dsp@92400000@linux,cma2shared-dma-poolpmu2arm,armv8-pmuv3 zpsci 2arm,psci-1.0smcsystem-controller 2fsl,imx-scu tx0rx0gip3$power-controller2fsl,imx8dl-scu-pdfsl,scu-pd clock-controller2fsl,imx8dxl-clkfsl,scu-clkgpio2fsl,imx8qxp-sc-gpioSpinctrl2fsl,imx8dxl-iomuxcdefaultMhoggrp0'<I@LkLusbotg1grp '!+usbotg2grp '!Heqosgrp'- , 3 9 6 5 4 : / 7 8 0 2 1 <flexspi0grp'y!x!{!z!}!|!~!!!!!!!!Nfec1grp'#*- , $`&`'`(`)`%``` `!`"``6lpspi3grp0'=@>@?@A@i2c2grp's!t!"cm40lpuartgrp'S R i2c3grp'v!u!lpuart0grp'\ ] usdhc1grp' A ! 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z  Pdisabledmailbox@5d280000]( z clock-controller@5d4000002fsl,imx8qxp-lpcg]@4O(hpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clk Iclock-controller@5d4100002fsl,imx8qxp-lpcg]A4O(hpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clk Jclock-controller@5d4200002fsl,imx8qxp-lpcg]B4O(hpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clk Kclock-controller@5d4300002fsl,imx8qxp-lpcg]C4O(hpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clk Lclock-controller@5d4400002fsl,imx8qxp-lpcg]D4O(hpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clk clock-controller@5d4500002fsl,imx8qxp-lpcg]E4O(hpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clk clock-controller@5d4600002fsl,imx8qxp-lpcg]F4O(hpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clk clock-controller@5d4700002fsl,imx8qxp-lpcg]G4O(hpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clk clock-conn-enet0-root 2fixed-clock沀conn_enet0_root_clkDclock-dummy 2fixed-clock clk_dummy*chosen/bus@5a000000/serial@5a060000memory@80000000memory@regulator-02regulator-fixed2Z2Zmux3_en Pregulator-12regulator-fixed fec1_supply2Z2Z 9  Pdisabledregulator-22regulator-fixedfec1_io_supplyw@w@ Q Pdisabledregulator-32regulator-fixed SD1_SPWR-- R 2regulator-adc-vref2regulator-fixed vref_1v8w@w@%regulator-42regulator-fixed mii-select2Z2Z S interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0ethernet1gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7mu1i2c2mmc0mmc1serial0device_typeregenable-methodnext-level-cacheclocks#cooling-cellsoperating-points-v2phandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsrangesno-mapreusablesizealloc-rangeslinux,cma-defaultmbox-namesmboxes#power-domain-cells#clock-cellsgpio-controller#gpio-cellspinctrl-namespinctrl-0fsl,pinslinux,keycodeswakeup-sourcetimeout-sec#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceclock-frequencyclock-output-names#dma-cellsdma-channelsdma-channel-maskpower-domainsclock-indicesclock-namesmemory-regionstatusassigned-clocksassigned-clock-ratesfsl,spi-only-use-cs1-selspi-max-frequencydma-namesdmas#pwm-cells#io-channel-cellsvref-supplyfsl,clk-sourcefsl,scu-indexfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dwordsrp-disablehnp-disableadp-disablepower-active-highdisable-over-current#index-cellsfsl,tx-d-calbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetrx-internal-delay-psnvmem-cellsnvmem-cell-namesreset-gpiosreset-assert-usqca,disable-smarteeevddio-supplyregulator-min-microvoltregulator-max-microvoltinterrupt-nameseee-broken-1000tqca,disable-hibernation-modereset-deassert-usreg-namesphysphy-namescdns,on-chip-buff-size#phy-cellsgpio-rangesspi-tx-bus-widthspi-rx-bus-width#mbox-cellsstdout-pathregulator-namegpioregulator-always-onenable-active-highoff-on-delay-us