Z8T(T$mediatek,mt2712-evbmediatek,mt2712 +!7MediaTek MT2712 evaluation boardopp_table0operating-points-v2=Hopp00P#WB@opp01P)׫WB@opp02P/D8@WB@opp_table1operating-points-v2=H opp00P#WB@opp01P)׫WB@opp02P/D8@WB@opp03P5w"@WB@opp04P; @WB@cpus+cpu-mapcluster0core0ecore1ecluster1core0ecpu@0icpuarm,cortex-a35uy%cpuintermediate Hcpu@1icpuarm,cortex-a35upsciy%cpuintermediate Hcpu@200icpuarm,cortex-a72upsciy'cpuintermediate   Hidle-statespscicpu-sleep-0arm,idle-statedP H cluster-sleep-0arm,idle-state^P H psci arm,psci-0.2smcdummy26m fixed-clock1AHdummyclk fixed-clock1AHoscillator-26m fixed-clockA1Nclk26mH*oscillator-32k fixed-clockA1Nclk32koscillator-50m fixed-clockA1Nclkfpcoscillator-aud0 fixed-clockA1c.Nclkaud_ext_i_0oscillator-aud1 fixed-clockA1 Nclkaud_ext_i_1oscillator-aud2 fixed-clockA1 @Nclkaud_ext_i_2oscillator-i2s0 fixed-clockA1ÀNclki2si0_mck_ioscillator-i2s1 fixed-clockA1ÀNclki2si1_mck_ioscillator-i2s2 fixed-clockA1ÀNclki2si2_mck_ioscillator-mclk fixed-clockA1ÀNclktdmin_mclk_itimerarm,armv8-timer 0a   syscon@10000000 mediatek,mt2712-topckgensysconuAHclock-controller@10001000 mediatek,mt2712-infracfgsysconuAlHsyscon@10003000mediatek,mt2712-pericfgsysconu0AHsyscfg_pctl_a@10005000%mediatek,mt2712-pctl-a-syscfgsysconuPHpinctrl@1000b000mediatek,mt2712-pinctrluy aH"eth-default-pinsH#tx_pinsGHIJKLrx_pinsNOPQRTmdio_pinsUVeth-sleep-pinsH$tx_pinsGHIJKLrx_pinsNOPQRTmdio_pinsUVusb0-iddig-pinsH)pins_iddig  usb1-iddig-pinsH1pins_iddig power-controller@10006000mediatek,mt2712-scpsyssyscon-u`0yeihgmmmfgvencjpgdecaudiovdecAHserial@1000f000*mediatek,mt2712-uartmediatek,mt6577-uartu ay baudbusJ  Otxrx Ydisabledrtc@10011000mediatek,mt2712-rtcu aspi@10013000mediatek,mt2712-spi-slaveu0 ayspi`p Ydisablediommu@10205000mediatek,mt2712-m4uu P aybclksyscon@10209000"mediatek,mt2712-apmixedsyssysconu Aiommu@1020a000mediatek,mt2712-m4uu  aybclk syscon@10220000mediatek,mt2712-mcucfgsysconu"AHinterrupt-controller@10220a80.mediatek,mt2712-sysirqmediatek,mt6577-sysirq u" @Hinterrupt-controller@10510000 arm,gic-400 @uQRTV a H dma-controller@110004002mediatek,mt2712-uart-dmamediatek,mt6577-uart-dmau  aghijklmnopqr y apdmaHadc@11001000mediatek,mt2712-auxadcuymainYokayserial@11002000*mediatek,mt2712-uartmediatek,mt6577-uartu  a[y baudbusJOtxrxYokayserial@11003000*mediatek,mt2712-uartmediatek,mt6577-uartu0 a\y baudbusJOtxrx Ydisabledserial@11004000*mediatek,mt2712-uartmediatek,mt6577-uartu@ a]y baudbusJOtxrx Ydisabledserial@11005000*mediatek,mt2712-uartmediatek,mt6577-uartuP a^y baudbusJOtxrx Ydisabledpwm@11006000mediatek,mt2712-pwmu` aMPyf  1topmainpwm1pwm2pwm3pwm4pwm5pwm6pwm7pwm8 Ydisabledi2c@11007000mediatek,mt2712-i2c up aTy  maindma+ Ydisabledi2c@11008000mediatek,mt2712-i2c u aUy  maindma+ Ydisabledi2c@11009000mediatek,mt2712-i2c u aVy  maindma+ Ydisabledspi@1100a000mediatek,mt2712-spi+u avylparent-clksel-clkspi-clk Ydisablednfi@1100e000mediatek,mt2712-nfcu a`ynfi_clkpad_clk+ Ydisabledecc@1100f000mediatek,mt2712-eccu a_y nfiecc_clk YdisabledHi2c@11010000mediatek,mt2712-i2c u aWy  maindma+ Ydisabledi2c@11011000mediatek,mt2712-i2c u aXy  maindma+ Ydisabledi2c@11013000mediatek,mt2712-i2c u0 aZy  maindma+ Ydisabledspi@11015000mediatek,mt2712-spi+uP aylparent-clksel-clkspi-clk Ydisabledspi@11016000mediatek,mt2712-spi+u` aylparent-clksel-clkspi-clk Ydisabledspi@10012000mediatek,mt2712-spi+u  aylparent-clksel-clkspi-clk Ydisabledspi@11018000mediatek,mt2712-spi+u aylparent-clksel-clkspi-clk Ydisabledserial@11019000*mediatek,mt2712-uartmediatek,mt6577-uartu a~y baudbusJ Otxrx Ydisabledstmmac-axi-config Hrx-queues-config-Hqueue0>Qitx-queues-configwH queue0>iqueue1>iqueue2>iethernet@1101c000mediatek,mt2712-gmacu amacirqU{}axiapbmac_mainptp_ref y"%`p= '2Yokay :rgmii-rxidC!N c"Wsdefaultsleep#$mdiosnps,dwmac-mdio+ethernet-phy@5ethernet-phy-id0243.0d90uH!mmc@11230000mediatek,mt2712-mmcu# aO y *,&sourcehclkbus_clksource_cg Ydisabledmmc@11240000mediatek,mt2712-mmcu$ aPy c'sourcehclksource_cg Ydisabledmmc@11250000mediatek,mt2712-mmcu% aQyc(sourcehclksource_cg Ydisabledusb@11271000#mediatek,mt2712-mtu3mediatek,mtu3 u'0( macippc az%&ynsys_ck +Yokay'(otgsdefault)usb@11270000'mediatek,mt2712-xhcimediatek,mtk-xhciu'mac a{ yn*sys_ckref_ckYokay+t-phy@11290000.mediatek,mt2712-tphymediatek,generic-tphy-v2+)Yokayusb-phy@0uy*refYokayH%usb-phy@8000uy*refYokayH&usb-phy@8700u y*refYokayH2usb@112c1000#mediatek,mt2712-mtu3mediatek,mtu3 u,0- macippc a,-.ynsys_ck +Yokay/0otg sdefault1usb@112c0000'mediatek,mt2712-xhcimediatek,mtk-xhciu,mac a yn*sys_ckref_ckYokayt-phy@112e0000.mediatek,mt2712-tphymediatek,generic-tphy-v2+.Yokayusb-phy@0uy*refYokayH,usb-phy@8000uy*refYokayH-usb-phy@8700u y*refYokayH.pcie@11700000mediatek,mt2712-pcieipci up/ port0port1+asu y#$ sys_ck0sys_ck1ahb_ck0ahb_ck12.pcie-phy0pcie-phy1' pcie@0,0ipci Ydisabledu+1`D3333interrupt-controllerH3pcie@1,0ipci Ydisabledu+1`D4444interrupt-controllerH4syscon@13000000mediatek,mt2712-mfgcfgsysconuAsyscon@14000000mediatek,mt2712-mmsyssysconuAH6larb@14021000mediatek,mt2712-smi-larbuR5_y66apbsmiHsmi@14022000mediatek,mt2712-smi-commonu y66apbsmiH5larb@14027000mediatek,mt2712-smi-larbupR7_y6,6,apbsmiHlarb@14030000mediatek,mt2712-smi-larbuR7_y6.6.apbsmiHsmi@14031000mediatek,mt2712-smi-commonuy6-6-apbsmiH7larb@14032000mediatek,mt2712-smi-larbu R7_y6868apbsmiHsyscon@15000000mediatek,mt2712-imgsyssysconuAH8larb@15001000mediatek,mt2712-smi-larbuR5_y88apbsmiHsyscon@15010000mediatek,mt2712-bdpsyssysconuAsyscon@16000000mediatek,mt2712-vdecsyssysconuAH9larb@16010000mediatek,mt2712-smi-larbuR5_y99apbsmiHsyscon@18000000mediatek,mt2712-vencsyssysconuAH:larb@18001000mediatek,mt2712-smi-larbuR5_y::apbsmiHlarb@18002000mediatek,mt2712-smi-larbu R5_y::apbsmiHsyscon@19000000!mediatek,mt2712-jpgdecsyssysconuAaliasesp/serial@11002000memory@40000000imemoryu@chosenxserial0:921600n8regulator-vproc-buck0regulator-fixed vproc_buck0B@B@Hregulator-vproc-buck1regulator-fixed vproc_buck1B@B@H extcon_iddiglinux,extcon-usb-gpio " H(extcon_iddig1linux,extcon-usb-gpio "H0regulator-usb-p0-vbusregulator-fixedp0_vbusLK@LK@ n" H'regulator-usb-p1-vbusregulator-fixedp1_vbusLK@LK@ n"H/regulator-usb-p2-vbusregulator-fixedp2_vbusLK@LK@ n"H+regulator-usb-p3-vbusregulator-fixedp3_vbusLK@LK@ n" compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltcpudevice_typeregclocksclock-namesproc-supplyoperating-points-v2cpu-idle-statesenable-methodentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramclock-frequency#clock-cellsclock-output-namesinterrupts#reset-cellsmediatek,pctl-regmappins-are-numberedgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxdrive-strengthinput-enableinput-disablebias-disablebias-pull-up#power-domain-cellsinfracfgdmasdma-namesstatusassigned-clocksassigned-clock-parentsmediatek,larbs#iommu-cellsdma-requests#dma-cells#io-channel-cells#pwm-cellsclock-divecc-enginesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,prioritysnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightinterrupt-namesmac-addresspower-domainsmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblclk_csrphy-modephy-handlemediatek,tx-delay-pssnps,reset-gpiopinctrl-namespinctrl-0pinctrl-1reg-namesphysmediatek,syscon-wakeuprangesvbus-supplyextcondr_modewakeup-sourcemediatek,u3p-dis-msk#phy-cellsenable-manual-drdphy-namesbus-rangeinterrupt-map-maskinterrupt-mapmediatek,smimediatek,larb-idserial0stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltid-gpioenable-active-highregulator-always-on