6]83H(3)STMicroelectronics STM32F746-DISCO board !st,stm32f746-discost,stm32f746interrupt-controller@e000e100!arm,armv7m-nvic,AR Vtimer@e000e010!arm,armv7m-systickR^okay esoc !simple-busl}timers@40000000!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@1!st,stm32-timer-triggerR ^disabledtimers@40000400!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@2!st,stm32-timer-triggerR ^disabledtimers@40000800!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@3!st,stm32-timer-triggerR ^disabledtimers@40000c00!st,stm32-timerR@  e^okay2timers@40001000!st,stm32-timersR@ eint ^disabledtimer@5!st,stm32-timer-triggerR ^disabledtimers@40001400!st,stm32-timersR@ eint ^disabledtimer@6!st,stm32-timer-triggerR ^disabledtimers@40001800!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@11!st,stm32-timer-triggerR  ^disabledtimers@40001c00!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimers@40002000!st,stm32-timersR@  eint ^disabledpwm !st,stm32-pwm ^disabledrtc@40002800 !st,stm32-rtcR@( e  l  ^disabledserial@40004400!st,stm32f7-uartR@D& e ^disabledserial@40004800!st,stm32f7-uartR@H' e ^disabledserial@40004c00!st,stm32f7-uartR@L4 e ^disabledserial@40005000!st,stm32f7-uartR@P5 e ^disabledi2c@40005400!st,stm32f7-i2cR@T  e^okaydefault i2c@40005800!st,stm32f7-i2cR@X!" e ^disabledi2c@40005c00!st,stm32f7-i2cR@\HI e ^disabledi2c@40006000!st,stm32f7-i2cR@`_` e ^disabledcec@40006c00 !st,stm32-cecR@l^e cechdmi-cec ^disabledserial@40007800!st,stm32f7-uartR@xR e ^disabledserial@40007c00!st,stm32f7-uartR@|S e ^disabledtimers@40010000!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@0!st,stm32-timer-triggerR ^disabledtimers@40010400!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@7!st,stm32-timer-triggerR ^disabledserial@40011000!st,stm32f7-uartR@% e^okaydefaultserial@40011400!st,stm32f7-uartR@G e ^disabledmmc@40011c00!arm,pl180arm,primecell%R@ e apb_pclkg<l ^disabledmmc@40012c00!arm,pl180arm,primecell%R@, e apb_pclk1<l^okayJ V defaultopendrain _ isyscon@40013800!st,stm32-syscfgsysconR@8Vinterrupt-controller@40013c00!st,stm32-exti,AR@<8 ()*>LVtimers@40014000!st,stm32-timersR@@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@8!st,stm32-timer-triggerR ^disabledtimers@40014400!st,stm32-timersR@D eint ^disabledpwm !st,stm32-pwm ^disabledtimers@40014800!st,stm32-timersR@H eint ^disabledpwm !st,stm32-pwm ^disabledpower-config@40007000!st,stm32-power-configsysconR@pVcrc@40023000!st,stm32f7-crcR@0 e  ^disabledrcc@40023800s!st,stm32f746-rccst,stm32-rccR@8e  B@Vdma-controller@40026000 !st,stm32-dmaR@` / e ^disableddma-controller@40026400 !st,stm32-dmaR@d 89:;<DEF e ^disabledusb@40040000!st,stm32f7-hsotgR@M eotg  @@@@ ^okayhost  usb2-phydefaultusb@50000000!st,stm32f4x9-fsotgRPC e'otg^okayhostdefaultpin-controller@40020000 }@0l!st,stm32f746-pinctrlgpio@40020000!,AR e-GPIOAgpio@40020400!,AR e-GPIOBgpio@40020800!,AR e-GPIOCVgpio@40020c00!,AR  e-GPIODVgpio@40021000!,AR e-GPIOEgpio@40021400!,AR e-GPIOFgpio@40021800!,AR e-GPIOGgpio@40021c00!,AR e-GPIOHgpio@40022000!,AR  e-GPIOIgpio@40022400!,AR$ e -GPIOJgpio@40022800!,AR( e -GPIOKcec-0pins:AK\usart1-0pins1: \iApins2: \usart1-1Vpins1: \iApins2:\i2c1-0Vpins:\KAusbotg-hs-0pins0:t          \iAusbotg-hs-1Vpins0:t "          \iAusbotg-fs-0Vpins : \iAsdio-pins-a-0V pins:( ) * + , 2 iAsdio-pins-od-a-0V pins1:( ) * + , iApins2:2 KAsdio-pins-b-0pins:i j   6 7 iAsdio-pins-od-b-0pins1:i j   6 iApins2:7 KAclocksclk-hse !fixed-clocky}x@V clk-lse !fixed-clockyclk-lsi !fixed-clocky}clk-i2s-ckin !fixed-clockylV chosenroot=/dev/ramserial0:115200n8memory@c0000000memoryRaliases/soc/serial@40011000usb-phy!usb-nop-xceiv e main_clkV vcc5v-otg-fs-regulator!regulator-fixed  vcc5_host1mmc_vcard!regulator-fixed mmc_vcard2Z2ZV #address-cells#size-cellsmodelcompatibleinterrupt-controller#interrupt-cellsregphandlestatusclocksinterrupt-parentrangesclock-names#pwm-cellsinterruptsassigned-clocksassigned-clock-parentsst,syscfgresetspinctrl-0pinctrl-namesi2c-scl-rising-time-nsi2c-scl-falling-time-nsarm,primecell-periphidmax-frequencyvmmc-supplycd-gpiospinctrl-1bus-width#reset-cells#clock-cellsassigned-clock-rates#dma-cellsst,mem2memg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modephysphy-namespins-are-numberedgpio-controller#gpio-cellsst,bank-namepinmuxslew-ratedrive-open-drainbias-disabledrive-push-pullclock-frequencybootargsstdout-pathdevice_typeserial0#phy-cellsgpioregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvolt