8( 5tgoogle,veyron-speedy-rev9google,veyron-speedy-rev8google,veyron-speedy-rev7google,veyron-speedy-rev6google,veyron-speedy-rev5google,veyron-speedy-rev4google,veyron-speedy-rev3google,veyron-speedy-rev2google,veyron-speedygoogle,veyronrockchip,rk3288&7Google Speedyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhopp-table-0operating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H ;a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр ;Drvbiuciuciu-driveciu-sample"  @-reset9okay@J\m  Zdefault mmc@ff0d0000rockchip,rk3288-dw-mshcр ;Eswbiuciuciu-driveciu-sample" ! @-reset9okay@\$:Edefault  mmc@ff0e0000rockchip,rk3288-dw-mshcр ;Ftxbiuciuciu-driveciu-sample" "@-reset 9disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр ;Guybiuciuciu-driveciu-sample" #@-reset9okay@JS:Edefault  saradc@ff100000rockchip,saradc $b;I[saradcapb_pclkW -saradc-apb 9disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclkt  ytxrx ,default !"#9okayec@0google,cros-ec-spi& default $-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb D*;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclkt ytxrx -default %&'( 9disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclktytxrx .default )*+,9okay7 flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;Mdefault -9okayJ2bdtpm@20infineon,slb9645tt yi2c@ff150000rockchip,rk3288-i2c ?i2c;Odefault . 9disabledi2c@ff160000rockchip,rk3288-i2c @i2c;Pdefault /9okayJ2b,ts3a227e@3b ti,ts3a227e;&0default 1htrackpad@15elan,ekth3000& default 23i2c@ff170000rockchip,rk3288-i2c Ai2c;Qdefault 4 9disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclktytxrxdefault  5679okaybluetoothdefault  89:brcm,bcm43540-bt ; ; ;- serial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclktytxrxdefault <9okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclkdefault =9okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclktytxrxdefault > 9disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclkt  ytxrxdefault ? 9disableddma-controller@ff250000arm,pl330arm,primecell%@"-H; apb_pclkhthermal-zonesreserve-thermal_u@cpu-thermal_du@tripscpu_alert0passivehAcpu_alert1ppassivehBcpu_crit_ criticalcooling-mapsmap0A0map1B0gpu-thermal_du@tripsgpu_alert08passivehCgpu_crit_ criticalcooling-mapsmap0C Dtsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk -tsadc-apbinitdefaultsleep EFEGH9okay #h@ethernet@ff290000rockchip,rk3288-gmac)>macirqeth_wake_irqG8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB -stmmaceth 9disabledusb@ff500000 generic-ehciP ;NHSusb9okay]usb@ff520000 generic-ohciR );NHSusb 9disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otgshostNI Susb2-phy{9okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otgshost@@ NJ Susb2-phy9okayzJusb@ff5c0000 generic-ehci\ ; 9disableddma-controller@ff600000arm,pl330arm,primecell`@"-H; apb_pclk 9disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;Ldefault K9okayJ2bdpmic@1brockchip,rk808xin32kwifibt_32kin&0default L!-9EQM]iu3MMhregulatorsDCDC_REG1vdd_arm q qh regulator-state-mem/DCDC_REG2vdd_gpu 5qhregulator-state-mem/DCDC_REG3 vcc135_ddrregulator-state-memHDCDC_REG4vcc_18w@w@hregulator-state-memH`w@LDO_REG1 vcc33_io2Z2Zh3regulator-state-memH`2ZLDO_REG3vdd_10B@B@regulator-state-memH`B@LDO_REG7vdd10_lcd_pwren_h&%&%regulator-state-mem/SWITCH_REG1 vcc33_lcdhcregulator-state-mem/LDO_REG6 vcc18_codecw@w@hdregulator-state-mem/LDO_REG4 vccio_sdw@2Zhregulator-state-mem/LDO_REG5 vcc33_sd2Z2Zhregulator-state-mem/LDO_REG8 vcc33_ccd2Z2Zregulator-state-mem/i2c@ff660000rockchip,rk3288-i2cf =i2c;Ndefault N9okayJ2b max98090@10maxim,max98090&Omclk;qdefault Phpwm@ff680000rockchip,rk3288-pwmh|default Q;_9okayhpwm@ff680010rockchip,rk3288-pwmh|default R;_9okayhpwm@ff680020rockchip,rk3288-pwmh |default S;_ 9disabledpwm@ff680030rockchip,rk3288-pwmh0|default T;_ 9disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controllerh hhpower-domain@9 ;chgfdehilkj$UVWXYZ[\]power-domain@11 ;op^_power-domain@12 ;`power-domain@13 ;abreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvGHjk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhGedp-phyrockchip,rk3288-dp-phy;h24m 9okayhxio-domains"rockchip,rk3288-io-voltage-domain9okay 3  ! /3 ?3 Mc Y ed rusbphyrockchip,rk3288-usb-phy9okayusb-phy@320  ;]phyclk -phy-resethJusb-phy@334 4;^phyclk -phy-resethHusb-phy@348 H;_phyclk -phy-resethIwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p O9okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif ;T mclkhclkteytx 6default fG 9disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s  5;Ri2s_clki2s_hclkteeytxrxdefault g  9okayhcrypto@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk -crypto-rstiommu@ff900800rockchip,iommu@ ; aclkiface  9disablediommu@ff914000rockchip,iommu @P ; aclkiface   9disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk h ilm -coreaxiahbvop@ff930000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop h def -axiahbdclk i9okayporth endpoint@0 jh~endpoint@1 khyendpoint@2 lhsendpoint@3 mhviommu@ff930300rockchip,iommu ; aclkiface h  9okayhivop@ff940000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop h  -axiahbdclk n9okayporth endpoint@0 ohendpoint@1 phzendpoint@2 qhtendpoint@3 rhwiommu@ff940300rockchip,iommu ; aclkiface h  9okayhnmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk h G 9disabledportsportendpoint@0 shlendpoint@1 thqlvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvdslcdc u h G 9disabledportsport@0endpoint@0 vhmendpoint@1 whrdp@ff970000rockchip,rk3288-dp@ b;icdppclkNxSdpo-dpG9okay portsport@0endpoint@0 yhkendpoint@1 zhpport@1endpoint@0 {hhdmi@ff980000rockchip,rk3288-dw-hdmi G g;hmniahbisfrcec h 9okaydefaultunwedge |}hportsportendpoint@0 ~hjendpoint@1 hovideo-codec@ff9a0000rockchip,rk3288-vpu   >vepuvdpu; aclkhclk  h iommu@ff9a0800rockchip,iommu ; aclkiface  h hiommu@ff9c0440rockchip,iommu @@@ o; aclkiface  9disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ >jobmmugpu;  h 9okay hDopp-table-1operating-points-v2hopp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000rockchip,rk3288-qossyscon haqos@ffaa0080rockchip,rk3288-qossyscon hbqos@ffad0000rockchip,rk3288-qossyscon hVqos@ffad0100rockchip,rk3288-qossyscon hWqos@ffad0180rockchip,rk3288-qossyscon hXqos@ffad0400rockchip,rk3288-qossyscon hYqos@ffad0480rockchip,rk3288-qossyscon hZqos@ffad0500rockchip,rk3288-qossyscon hUqos@ffad0800rockchip,rk3288-qossyscon h[qos@ffad0880rockchip,rk3288-qossyscon h\qos@ffad0900rockchip,rk3288-qossyscon h]qos@ffae0000rockchip,rk3288-qossyscon h`qos@ffaf0000rockchip,rk3288-qossyscon h^qos@ffaf0080rockchip,rk3288-qossyscon h_dma-controller@ffb20000arm,pl330arm,primecell@"-H; apb_pclkheefuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400 ) >@ @ `   hpinctrlrockchip,rk3288-pinctrlGdefaultsleep gpio@ff750000rockchip,gpio-banku Q;@ O _ ) > kPMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh0gpio@ff780000rockchip,gpio-bankx R;A O _ ) >gpio@ff790000rockchip,gpio-banky S;B O _ ) >Z kCONFIG0CONFIG1CONFIG2CONFIG3PWRLIMIT#_CPUEMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENhgpio@ff7a0000rockchip,gpio-bankz T;C O _ ) > kFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank{ U;D O _ ) > kUART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEh;gpio@ff7c0000rockchip,gpio-bank| V;E O _ ) >A kSPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhgpio@ff7d0000rockchip,gpio-bank} W;F O _ ) > kI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhOgpio@ff7e0000rockchip,gpio-bank~ X;G O _ ) > kLCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVS_OKEDP_HOTPLUGDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio@ff7f0000rockchip,gpio-bank Y;H O _ ) >^ kRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 {hdmi-cec-c7 {hdmi-ddc {h|hdmi-ddc-unwedge {h}vcc50-hdmi-en {hpcfg-output-low hpcfg-pull-up hpcfg-pull-down hpcfg-pull-none hpcfg-pull-none-12ma  hsuspendglobal-pwroff {hddrio-pwroff {hddr0-retention {hddr1-retention {suspend-l-wake {hsuspend-l-sleep {hedpedp-hpd { i2c0i2c0-xfer {hKi2c1i2c1-xfer {h-i2c2i2c2-xfer {  hNi2c3i2c3-xfer {h.i2c4i2c4-xfer {h/i2c5i2c5-xfer {h4i2s0i2s0-bus` {hglcdclcdc-ctl@ {husdmmcsdmmc-clk {hsdmmc-cmd {hsdmmc-cd {sdmmc-bus1 {sdmmc-bus4@ {hsdmmc-cd-disabled {hsdmmc-cd-pin {hsdio0sdio0-bus1 {sdio0-bus4@ {hsdio0-cmd {hsdio0-clk {hsdio0-cd {sdio0-wp {sdio0-pwr {sdio0-bkpwr {sdio0-int {wifienable-h {hbt-enable-l {h9bt-host-wake {bt-host-wake-l {h8bt-dev-wake-sleep {bt-dev-wake-awake {bt-dev-wake {h:sdio1sdio1-bus1 {sdio1-bus4@ {sdio1-cd {sdio1-wp {sdio1-bkpwr {sdio1-int {sdio1-cmd {sdio1-clk {sdio1-pwr { emmcemmc-clk {hemmc-cmd {hemmc-pwr { emmc-bus1 {emmc-bus4@ {emmc-bus8 {hemmc-reset { hspi0spi0-clk { h spi0-cs0 { h#spi0-tx {h!spi0-rx {h"spi0-cs1 {spi1spi1-clk { h%spi1-cs0 { h(spi1-rx {h'spi1-tx {h&spi2spi2-cs1 {spi2-clk {h)spi2-cs0 {h,spi2-rx {h+spi2-tx { h*uart0uart0-xfer {h5uart0-cts {h6uart0-rts {h7uart1uart1-xfer { h<uart1-cts { uart1-rts { uart2uart2-xfer {h=uart3uart3-xfer {h>uart3-cts { uart3-rts { uart4uart4-xfer {h?uart4-cts { uart4-rts { tsadcotp-pin { hEotp-out { hFpwm0pwm0-pin {hQpwm1pwm1-pin {hRpwm2pwm2-pin {hSpwm3pwm3-pin {hTgmacrgmii-pins { rmii-pins {spdifspdif-tx { hfpcfg-pull-none-drv-8ma  hpcfg-pull-up-drv-8ma  pcfg-output-high hbuttonspwr-key-l {hap-lid-int-l {hpmicpmic-int-l {hLdvs-1 { dvs-2 {rebootap-warm-reset-h { hrecovery-switchrec-mode-l { tpmtpm-int-h {write-protectfw-wp-ap {codechp-det {hint-codec {hPmic-det { hheadsetts3a227e-int-l {h1backlightbl_pwr_en { hbl-en {hlcdlcd-en {havdd-1v8-disp-en { hchargerac-present-ap {hcros-ecec-int {h$trackpadtrackpad-int {h2usb-hosthost1-pwr-en { husbotg-pwren-h { hbuck-5vdrv-5v {hchosen serial2:115200n8memorymemorypower-button gpio-keysdefault power Power 0 t dgpio-restart gpio-restart 0 default  emmc-pwrseqmmc-pwrseq-emmc default  hsdio-pwrseqmmc-pwrseq-simple; ext_clockdefault  ;hvcc-5vregulator-fixedvcc_5vLK@LK@  ' : default hMvcc33-sysregulator-fixed vcc33_sys2Z2Z hvcc50-hdmiregulator-fixed vcc50_hdmi M ' :default vdd-logicpwm-regulator vdd_logic ? D O{ c~psound!rockchip,rockchip-audio-max98090default  vVEYRON-I2S   O O   backlight-regulatorregulator-fixed ' : default backlight_regulator  :hpanel-regulatorregulator-fixed ' : default panel_regulator hvcc18-lcdregulator-fixed ' : default  vcc18_lcd backlightpwm-backlight  - D ] default  ?B@ j    hpanelinnolux,n116bge9okay  panel-timingl V  <       portsportendpoint h{gpio-charger gpio-charger mains 0default lid-switch gpio-keysdefault lid Lid 0  $ vccsysregulator-fixedvccsyshvcc5-host1-regulatorregulator-fixed ' :0 default  vcc5_host1vcc5v-otg-regulatorregulator-fixed ' :0 default  vcc5_host2 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-params#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type