8( google,veyron-minnie-rev4google,veyron-minnie-rev3google,veyron-minnie-rev2google,veyron-minnie-rev1google,veyron-minnie-rev0google,veyron-minniegoogle,veyronrockchip,rk3288&7Google Minniealiases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhopp-table-0operating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H ;a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр ;Drvbiuciuciu-driveciu-sample"  @-reset9okay@J\m  Zdefault mmc@ff0d0000rockchip,rk3288-dw-mshcр ;Eswbiuciuciu-driveciu-sample" ! @-reset9okay@\$:Edefault  mmc@ff0e0000rockchip,rk3288-dw-mshcр ;Ftxbiuciuciu-driveciu-sample" "@-reset 9disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр ;Guybiuciuciu-driveciu-sample" #@-reset9okay@JS:Edefault  saradc@ff100000rockchip,saradc $b;I[saradcapb_pclkW -saradc-apb 9disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclkt  ytxrx ,default !"#9okayec@0google,cros-ec-spi& default $-i2c-tunnelgoogle,cros-ec-i2c-tunnelbq27500@55 ti,bq27500Ukeyboard-controllergoogle,cros-ec-keyb D;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclkt ytxrx -default %&'( 9disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclktytxrx .default )*+,9okay flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;Mdefault -9okay!29dtpm@20infineon,slb9645tt Pi2c@ff150000rockchip,rk3288-i2c ?i2c;Odefault .9okay!29,touchscreen@10elan,ekth3500&/default 01 h/t22i2c@ff160000rockchip,rk3288-i2c @i2c;Pdefault 39okay!29,ts3a227e@3b ti,ts3a227e;&4default 5htrackpad@15elan,ekth3000& default 67i2c@ff170000rockchip,rk3288-i2c Ai2c;Qdefault 8 9disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclktytxrxdefault  9:;9okaybluetoothdefault  <=>brcm,bcm43540-bt ? ? ?-serial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclktytxrxdefault @9okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclkdefault A9okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclktytxrxdefault B 9disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclkt  ytxrxdefault C 9disableddma-controller@ff250000arm,pl330arm,primecell%@*E; apb_pclkhthermal-zonesreserve-thermal\rDcpu-thermal\drDtripscpu_alert0ppassivehEcpu_alert1$passivehFcpu_crit criticalcooling-mapsmap0E0map1F0gpu-thermal\drDtripsgpu_alert04passivehGgpu_crit criticalcooling-mapsmap0G Htsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk -tsadc-apbinitdefaultsleep IJIKH9okay  hDethernet@ff290000rockchip,rk3288-gmac);macirqeth_wake_irqK8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB -stmmaceth 9disabledusb@ff500000 generic-ehciP ;KLPusb9okayZusb@ff520000 generic-ohciR );KLPusb 9disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otgphostKM Pusb2-phyx9okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otgphost@@ KN Pusb2-phy9okayzNusb@ff5c0000 generic-ehci\ ; 9disableddma-controller@ff600000arm,pl330arm,primecell`@*E; apb_pclk 9disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;Ldefault O9okay!29dpmic@1brockchip,rk808xin32kwifibt_32kin&4default  PQR*6BNSZfr7SShregulatorsDCDC_REG1vdd_arm q qh regulator-state-mem,DCDC_REG2vdd_gpu 5qhregulator-state-mem,DCDC_REG3 vcc135_ddrregulator-state-memEDCDC_REG4vcc_18w@w@hregulator-state-memE]w@LDO_REG1 vcc33_io2Z2Zh7regulator-state-memE]2ZLDO_REG3vdd_10B@B@regulator-state-memE]B@LDO_REG7vdd10_lcd_pwren_h&%&%regulator-state-mem,SWITCH_REG1 vcc33_lcdhiregulator-state-mem,LDO_REG6 vcc18_codecw@w@hjregulator-state-mem,LDO_REG4 vccio_sdw@2Zhregulator-state-mem,LDO_REG5 vcc33_sd2Z2Zhregulator-state-mem,LDO_REG8 vcc33_ccd2Z2Zregulator-state-mem,LDO_REG22Z2Z vcc33_touchh2regulator-state-mem,SWITCH_REG2 vcc5v_touchregulator-state-mem,i2c@ff660000rockchip,rk3288-i2cf =i2c;Ndefault T9okay!29 max98090@10maxim,max98090&Umclk;qdefault Vhpwm@ff680000rockchip,rk3288-pwmhydefault W;_9okayhpwm@ff680010rockchip,rk3288-pwmhydefault X;_9okayhpwm@ff680020rockchip,rk3288-pwmh ydefault Y;_ 9disabledpwm@ff680030rockchip,rk3288-pwmh0ydefault Z;_ 9disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controllerh hnpower-domain@9 ;chgfdehilkj$[\]^_`abcpower-domain@11 ;opdepower-domain@12 ;fpower-domain@13 ;ghreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvKHjk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhKedp-phyrockchip,rk3288-dp-phy;h24m9okayh~io-domains"rockchip,rk3288-io-voltage-domain9okay 7   ,7 <7 Ji V bj ousbphyrockchip,rk3288-usb-phy9okayusb-phy@320 ;]phyclk -phy-resethNusb-phy@3344;^phyclk -phy-resethLusb-phy@348H;_phyclk -phy-resethMwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p O9okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif };T mclkhclktkytx 6default lK 9disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s } 5;Ri2s_clki2s_hclktkkytxrxdefault m  9okayhcrypto@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk -crypto-rstiommu@ff900800rockchip,iommu@ ; aclkiface  9disablediommu@ff914000rockchip,iommu @P ; aclkiface   9disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk n ilm -coreaxiahbvop@ff930000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop n def -axiahbdclk o9okayporth endpoint@0 phendpoint@1 qhendpoint@2 rhyendpoint@3 sh|iommu@ff930300rockchip,iommu ; aclkiface n  9okayhovop@ff940000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop n  -axiahbdclk t9okayporth endpoint@0 uhendpoint@1 vhendpoint@2 whzendpoint@3 xh}iommu@ff940300rockchip,iommu ; aclkiface n  9okayhtmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk n K 9disabledportsportendpoint@0 yhrendpoint@1 zhwlvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvdslcdc { n K 9disabledportsport@0endpoint@0 |hsendpoint@1 }hxdp@ff970000rockchip,rk3288-dp@ b;icdppclkK~Pdpo-dpK9okaydefault portsport@0endpoint@0 hqendpoint@1 hvport@1endpoint@0 hhdmi@ff980000rockchip,rk3288-dw-hdmi }K g;hmniahbisfrcec n 9okaydefaultunwedge hportsportendpoint@0 hpendpoint@1 huvideo-codec@ff9a0000rockchip,rk3288-vpu   ;vepuvdpu; aclkhclk  n iommu@ff9a0800rockchip,iommu ; aclkiface  n hiommu@ff9c0440rockchip,iommu @@@ o; aclkiface  9disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ ;jobmmugpu;  n 9okay hHopp-table-1operating-points-v2hopp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000rockchip,rk3288-qossyscon hgqos@ffaa0080rockchip,rk3288-qossyscon hhqos@ffad0000rockchip,rk3288-qossyscon h\qos@ffad0100rockchip,rk3288-qossyscon h]qos@ffad0180rockchip,rk3288-qossyscon h^qos@ffad0400rockchip,rk3288-qossyscon h_qos@ffad0480rockchip,rk3288-qossyscon h`qos@ffad0500rockchip,rk3288-qossyscon h[qos@ffad0800rockchip,rk3288-qossyscon haqos@ffad0880rockchip,rk3288-qossyscon hbqos@ffad0900rockchip,rk3288-qossyscon hcqos@ffae0000rockchip,rk3288-qossyscon hfqos@ffaf0000rockchip,rk3288-qossyscon hdqos@ffaf0080rockchip,rk3288-qossyscon hedma-controller@ffb20000arm,pl330arm,primecell@*E; apb_pclkhkefuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  1@ @ `   hpinctrlrockchip,rk3288-pinctrlKdefaultsleep gpio@ff750000rockchip,gpio-banku Q;@ B R  1 ^PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh4gpio@ff780000rockchip,gpio-bankx R;A B R  1gpio@ff790000rockchip,gpio-banky S;B B R  1 ^CONFIG0CONFIG1CONFIG2CONFIG3PROCHOT#EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TPh/gpio@ff7a0000rockchip,gpio-bankz T;C B R  1 ^FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank{ U;D B R  1 ^UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKdev_wakeWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEh?gpio@ff7c0000rockchip,gpio-bank| V;E B R  1U ^Volum_Up#Volum_Down#SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhgpio@ff7d0000rockchip,gpio-bank} W;F B R  1 ^I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhUgpio@ff7e0000rockchip,gpio-bank~ X;G B R  1 ^LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVS_OKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio@ff7f0000rockchip,gpio-bank Y;H B R  1^ ^RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 nhdmi-cec-c7 nhdmi-ddc nhhdmi-ddc-unwedge nhvcc50-hdmi-en nhpcfg-output-low |hpcfg-pull-up hpcfg-pull-down hpcfg-pull-none hpcfg-pull-none-12ma  hsuspendglobal-pwroff nhddrio-pwroff nhddr0-retention nhddr1-retention nsuspend-l-wake nhsuspend-l-sleep nhedpedp-hpd n hi2c0i2c0-xfer nhOi2c1i2c1-xfer nh-i2c2i2c2-xfer n  hTi2c3i2c3-xfer nh.i2c4i2c4-xfer nh3i2c5i2c5-xfer nh8i2s0i2s0-bus` nhmlcdclcdc-ctl@ nh{sdmmcsdmmc-clk nhsdmmc-cmd nhsdmmc-cd nsdmmc-bus1 nsdmmc-bus4@ nhsdmmc-cd-disabled nhsdmmc-cd-pin nhsdio0sdio0-bus1 nsdio0-bus4@ nhsdio0-cmd nhsdio0-clk nhsdio0-cd nsdio0-wp nsdio0-pwr nsdio0-bkpwr nsdio0-int nwifienable-h nhbt-enable-l nh=bt-host-wake nbt-host-wake-l nh<bt-dev-wake-sleep nbt-dev-wake-awake nbt-dev-wake nh>sdio1sdio1-bus1 nsdio1-bus4@ nsdio1-cd nsdio1-wp nsdio1-bkpwr nsdio1-int nsdio1-cmd nsdio1-clk nsdio1-pwr n emmcemmc-clk nhemmc-cmd nhemmc-pwr n emmc-bus1 nemmc-bus4@ nemmc-bus8 nhemmc-reset n hspi0spi0-clk n h spi0-cs0 n h#spi0-tx nh!spi0-rx nh"spi0-cs1 nspi1spi1-clk n h%spi1-cs0 n h(spi1-rx nh'spi1-tx nh&spi2spi2-cs1 nspi2-clk nh)spi2-cs0 nh,spi2-rx nh+spi2-tx n h*uart0uart0-xfer nh9uart0-cts nh:uart0-rts nh;uart1uart1-xfer n h@uart1-cts n uart1-rts n uart2uart2-xfer nhAuart3uart3-xfer nhBuart3-cts n uart3-rts n uart4uart4-xfer nhCuart4-cts n uart4-rts n tsadcotp-pin n hIotp-out n hJpwm0pwm0-pin nhWpwm1pwm1-pin nhXpwm2pwm2-pin nhYpwm3pwm3-pin nhZgmacrgmii-pins n rmii-pins nspdifspdif-tx n hlpcfg-pull-none-drv-8ma  hpcfg-pull-up-drv-8ma  pcfg-output-high hbuttonspwr-key-l nhap-lid-int-l nhvolum-down-l n hvolum-up-l n hpmicpmic-int-l nhPdvs-1 n hQdvs-2 nhRrebootap-warm-reset-h n hrecovery-switchrec-mode-l n tpmtpm-int-h nwrite-protectfw-wp-ap ncodechp-det nhint-codec nhVmic-det n hheadsetts3a227e-int-l nh5backlightbl_pwr_en n hbl-en nhlcdlcd-en nhavdd-1v8-disp-en n hchargerac-present-ap nhcros-ecec-int nh$trackpadtrackpad-int nh6usb-hosthost1-pwr-en n husbotg-pwren-h n hbuck-5vdrv-5v nhprochotgpio-prochot ntouchscreentouch-int nh0touch-rst nh1chosen serial2:115200n8memorymemorypower-button gpio-keysdefault power Power 4 t dgpio-restart gpio-restart 4 default  emmc-pwrseqmmc-pwrseq-emmc default h/ hsdio-pwrseqmmc-pwrseq-simple; ext_clockdefault  h?hvcc-5vregulator-fixedvcc_5vLK@LK@   ! default hSvcc33-sysregulator-fixed vcc33_sys2Z2Z hvcc50-hdmiregulator-fixed vcc50_hdmi S  !default vdd-logicpwm-regulator vdd_logic & + 6{ J~psound!rockchip,rockchip-audio-max98090default  ]VEYRON-I2S l  U U   backlight-regulatorregulator-fixed  !/ default backlight_regulator  :hpanel-regulatorregulator-fixed  ! default panel_regulator hvcc18-lcdregulator-fixed  !/ default  vcc18_lcd backlightpwm-backlight   + D default  &B@ Q  f  whpanelauo,b101ean019okay w panel-timing@         portsportendpoint hgpio-charger gpio-charger mains 4default lid-switch gpio-keysdefault lid Lid 4   vccsysregulator-fixedvccsyshvcc5-host1-regulatorregulator-fixed  !4 default  vcc5_host1vcc5v-otg-regulatorregulator-fixed  !4 default  vcc5_host2volume-buttons gpio-keysdefault volum_down Volum_down   r dvolum_up Volum_up   s d #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-buskeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreset-gpiosvcc33-supplyvccio-supplyti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-params#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenvactivevfront-porchvback-porchvsync-lencharger-typelinux,input-type