m8( uKgoogle,veyron-jerry-rev15google,veyron-jerry-rev14google,veyron-jerry-rev13google,veyron-jerry-rev12google,veyron-jerry-rev11google,veyron-jerry-rev10google,veyron-jerry-rev7google,veyron-jerry-rev6google,veyron-jerry-rev5google,veyron-jerry-rev4google,veyron-jerry-rev3google,veyron-jerrygoogle,veyronrockchip,rk3288& 7Google Jerryaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhopp-table-0operating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H ;a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр ;Drvbiuciuciu-driveciu-sample"  @-reset9okay@J\m  Zdefault mmc@ff0d0000rockchip,rk3288-dw-mshcр ;Eswbiuciuciu-driveciu-sample" ! @-reset9okay@\$:Edefault  wifi@1marvell,sd8897S$g           $g           $g           $g           $g           $g           $g           $g           $g            $g            $g            $g            $g            q:$          :(          :,          :0          :4          :8          :<          :@          :d          :h          :l          :p          :t          :x          :|          :          :          :        :        <6:        :        :        :        :        mmc@ff0e0000rockchip,rk3288-dw-mshcр ;Ftxbiuciuciu-driveciu-sample" "@-reset 9disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр ;Guybiuciuciu-driveciu-sample" #@-reset9okay@J:Edefault  saradc@ff100000rockchip,saradc $;I[saradcapb_pclkW -saradc-apb 9disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclk  txrx ,default !"#9okayec@0google,cros-ec-spi & default $'-i2c-tunnelgoogle,cros-ec-i2c-tunnel9sbs-battery@bsbs,sbs-battery K_keyboard-controllergoogle,cros-ec-keybt D;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclk txrx -default %&'( 9disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclktxrx .default )*+,9okay flash@0jedec,spi-nor'i2c@ff140000rockchip,rk3288-i2c >i2c;Mdefault -9okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c;Odefault . 9disabledi2c@ff160000rockchip,rk3288-i2c @i2c;Pdefault /09okay2,ts3a227e@3b ti,ts3a227e;&1default 2htrackpad@15elan,ekth3000& #3.trackpad@2c hid-over-i2c& ,< #3.i2c@ff170000rockchip,rk3288-i2c Ai2c;Qdefault 4 9disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7KU;MUbaudclkapb_pclktxrxdefault  5679okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8KU;NVbaudclkapb_pclktxrxdefault 89okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9KU;OWbaudclkapb_pclkdefault 99okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :KU;PXbaudclkapb_pclktxrxdefault : 9disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;KU;QYbaudclkapb_pclk  txrxdefault ; 9disableddma-controller@ff250000arm,pl330arm,primecell%@bm; apb_pclkhthermal-zonesreserve-thermal<cpu-thermald<tripscpu_alert0ppassiveh=cpu_alert1$passiveh>cpu_crit criticalcooling-mapsmap0=0map1>0gpu-thermald<tripsgpu_alert04passiveh?gpu_crit criticalcooling-mapsmap0? @tsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk -tsadc-apbinitdefaultsleep ABA(C5H9okayLch<ethernet@ff290000rockchip,rk3288-gmac)~macirqeth_wake_irq(C8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB -stmmaceth 9disabledusb@ff500000 generic-ehciP ;Dusb9okayusb@ff520000 generic-ohciR );Dusb 9disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otghostE usb2-phy9okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otghost @@ F usb2-phy9okayz)Fusb@ff5c0000 generic-ehci\ ; 9disableddma-controller@ff600000arm,pl330arm,primecell`@bm; apb_pclk 9disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;Ldefault G9okay2dpmic@1brockchip,rk808xin32kwifibt_32kin&1default  HIJ@.amyK3KK hregulatorsDCDC_REG1vdd_arm"4 qL dqh regulator-state-memyDCDC_REG2vdd_gpu"4 5Ldqhregulator-state-memyDCDC_REG3 vcc135_ddr"regulator-state-memDCDC_REG4vcc_18"4w@Lw@hregulator-state-memw@LDO_REG1 vcc33_io"42ZL2Zh3regulator-state-mem2ZLDO_REG3vdd_10"4B@LB@regulator-state-memB@LDO_REG7vdd10_lcd_pwren_h"4&%L&%regulator-state-memySWITCH_REG1 vcc33_lcd"haregulator-state-memyLDO_REG6 vcc18_codec"4w@Lw@hbregulator-state-memyLDO_REG4 vccio_sd4w@L2Zhregulator-state-memyLDO_REG5 vcc33_sd42ZL2Zhregulator-state-memyLDO_REG8 vcc33_ccd"42ZL2Zregulator-state-memyLDO_REG2mic_vcc"4w@Lw@regulator-state-memyi2c@ff660000rockchip,rk3288-i2cf =i2c;Ndefault L9okay2 max98090@10maxim,max98090&Mmclk;qdefault Nhpwm@ff680000rockchip,rk3288-pwmhdefault O;_9okayhpwm@ff680010rockchip,rk3288-pwmhdefault P;_9okayhpwm@ff680020rockchip,rk3288-pwmh default Q;_ 9disabledpwm@ff680030rockchip,rk3288-pwmh0default R;_ 9disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controllerh) hfpower-domain@9 ;chgfdehilkj$STUVWXYZ[power-domain@11 ;op\]power-domain@12 ;^power-domain@13 ;_`reboot-modesyscon-reboot-modeRBRB RB  RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv(C )Hjk$ 6#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhCedp-phyrockchip,rk3288-dp-phy;h24m K9okayhvio-domains"rockchip,rk3288-io-voltage-domain9okay V3 ` k y3 3 a  b usbphyrockchip,rk3288-usb-phy9okayusb-phy@320 K ;]phyclk -phy-resethFusb-phy@334 K4;^phyclk -phy-resethDusb-phy@348 KH;_phyclk -phy-resethEwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p O9okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif ;T mclkhclkctx 6default d(C 9disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s  5;Ri2s_clki2s_hclkcctxrxdefault e  9okayhcrypto@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk -crypto-rstiommu@ff900800rockchip,iommu@ ; aclkiface  9disablediommu@ff914000rockchip,iommu @P ; aclkiface   9disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk 8f ilm -coreaxiahbvop@ff930000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop 8f def -axiahbdclk Fg9okayporth endpoint@0 Mhh}endpoint@1 Mihxendpoint@2 Mjhqendpoint@3 Mkhtiommu@ff930300rockchip,iommu ; aclkiface 8f  9okayhgvop@ff940000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop 8f  -axiahbdclk Fl9okayporth endpoint@0 Mmh~endpoint@1 Mnhyendpoint@2 Mohrendpoint@3 Mphuiommu@ff940300rockchip,iommu ; aclkiface 8f  9okayhlmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk 8f (C 9disabledportsportendpoint@0 Mqhjendpoint@1 Mrholvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvdslcdc s 8f (C 9disabledportsport@0endpoint@0 Mthkendpoint@1 Muhpdp@ff970000rockchip,rk3288-dp@ b;icdppclkvdpo-dp(C9okaydefault wportsport@0endpoint@0 Mxhiendpoint@1 Myhnport@1endpoint@0 Mzhhdmi@ff980000rockchip,rk3288-dw-hdmiU (C g;hmniahbisfrcec 8f 9okaydefaultunwedge {|hportsportendpoint@0 M}hhendpoint@1 M~hmvideo-codec@ff9a0000rockchip,rk3288-vpu   ~vepuvdpu; aclkhclk F 8f iommu@ff9a0800rockchip,iommu ; aclkiface  8f hiommu@ff9c0440rockchip,iommu @@@ o; aclkiface  9disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ ~jobmmugpu;  8f 9okay ]h@opp-table-1operating-points-v2hopp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000rockchip,rk3288-qossyscon h_qos@ffaa0080rockchip,rk3288-qossyscon h`qos@ffad0000rockchip,rk3288-qossyscon hTqos@ffad0100rockchip,rk3288-qossyscon hUqos@ffad0180rockchip,rk3288-qossyscon hVqos@ffad0400rockchip,rk3288-qossyscon hWqos@ffad0480rockchip,rk3288-qossyscon hXqos@ffad0500rockchip,rk3288-qossyscon hSqos@ffad0800rockchip,rk3288-qossyscon hYqos@ffad0880rockchip,rk3288-qossyscon hZqos@ffad0900rockchip,rk3288-qossyscon h[qos@ffae0000rockchip,rk3288-qossyscon h^qos@ffaf0000rockchip,rk3288-qossyscon h\qos@ffaf0080rockchip,rk3288-qossyscon h]dma-controller@ffb20000arm,pl330arm,primecell@bm; apb_pclkhcefuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400 i ~@ @ `   hpinctrlrockchip,rk3288-pinctrl(Cdefaultsleep gpio@ff750000rockchip,gpio-banku Q;@   i ~ PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFAULT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh1gpio@ff780000rockchip,gpio-bankx R;A   i ~gpio@ff790000rockchip,gpio-banky S;B   i ~M CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENhgpio@ff7a0000rockchip,gpio-bankz T;C   i ~ FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank{ U;D   i ~ UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEhgpio@ff7c0000rockchip,gpio-bank| V;E   i ~A SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhgpio@ff7d0000rockchip,gpio-bank} W;F   i ~ I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhMgpio@ff7e0000rockchip,gpio-bank~ X;G   i ~ LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKEDP_HPDDVS1nFAULT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio@ff7f0000rockchip,gpio-bank Y;H   i ~^ RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc h{hdmi-ddc-unwedge h|vcc50-hdmi-en hpcfg-output-low hpcfg-pull-up hpcfg-pull-down hpcfg-pull-none hpcfg-pull-none-12ma  hsuspendglobal-pwroff hddrio-pwroff hddr0-retention hddr1-retention suspend-l-wake hsuspend-l-sleep hedpedp-hpd  hwi2c0i2c0-xfer hGi2c1i2c1-xfer h-i2c2i2c2-xfer   hLi2c3i2c3-xfer h.i2c4i2c4-xfer h/i2c5i2c5-xfer h4i2s0i2s0-bus` helcdclcdc-ctl@ hssdmmcsdmmc-clk hsdmmc-cmd hsdmmc-cd sdmmc-bus1 sdmmc-bus4@ hsdmmc-cd-disabled hsdmmc-cd-pin hsdio0sdio0-bus1 sdio0-bus4@ hsdio0-cmd hsdio0-clk hsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h hbt-enable-l bt-host-wake bt-host-wake-l bt-dev-wake-sleep hbt-dev-wake-awake hbt-dev-wake sdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk hemmc-cmd hemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 hemmc-reset  hspi0spi0-clk  h spi0-cs0  h#spi0-tx h!spi0-rx h"spi0-cs1 spi1spi1-clk  h%spi1-cs0  h(spi1-rx h'spi1-tx h&spi2spi2-cs1 spi2-clk h)spi2-cs0 h,spi2-rx h+spi2-tx  h*uart0uart0-xfer h5uart0-cts h6uart0-rts h7uart1uart1-xfer  h8uart1-cts  uart1-rts  uart2uart2-xfer h9uart3uart3-xfer h:uart3-cts  uart3-rts  uart4uart4-xfer h;uart4-cts  uart4-rts  tsadcotp-pin hAotp-out hBpwm0pwm0-pin hOpwm1pwm1-pin hPpwm2pwm2-pin hQpwm3pwm3-pin hRgmacrgmii-pins  rmii-pins spdifspdif-tx  hdpcfg-pull-none-drv-8ma  hpcfg-pull-up-drv-8ma  pcfg-output-high hbuttonspwr-key-l hap-lid-int-l hpmicpmic-int-l hHdvs-1  hIdvs-2 hJrebootap-warm-reset-h hrecovery-switchrec-mode-l tpmtpm-int-h write-protectfw-wp-ap codechp-det hint-codec hNmic-det  hheadsetts3a227e-int-l h2backlightbl_pwr_en  hbl-en hlcdlcd-en havdd-1v8-disp-en  hchargerac-present-ap hcros-ecec-int h$trackpadtrackpad-int h0usb-hosthost1-pwr-en husbotg-pwren-h hbuck-5vdrv-5v hchosen serial2:115200n8memorymemorypower-button gpio-keysdefault power $Power 1 *t 5d.gpio-restart gpio-restart 1 default  Gemmc-pwrseqmmc-pwrseq-emmc default P hsdio-pwrseqmmc-pwrseq-simple; ext_clockdefault  Phvcc-5vregulator-fixedvcc_5v"4LK@LLK@ \ g z default hKvcc33-sysregulator-fixed vcc33_sys"42ZL2Z \hvcc50-hdmiregulator-fixed vcc50_hdmi" \K g zdefault vdd-logicpwm-regulator vdd_logic   { "4~Lpdsound!rockchip,rockchip-audio-max98090default  VEYRON-I2S   M M   6backlight-regulatorregulator-fixed g z default backlight_regulator \ J:hpanel-regulatorregulator-fixed g z default panel_regulator \hvcc18-lcdregulator-fixed g z default  vcc18_lcd" \backlightpwm-backlight [ m  default  B@   hpanelinnolux,n116bge9okay  panel-timingl V  <    ' 4  @  Jportsportendpoint Mhzgpio-charger gpio-charger Wmains 1default lid-switch gpio-keysdefault lid $Lid 1. * d 5vccsysregulator-fixedvccsys"hvcc5-host1-regulatorregulator-fixed g z1 default  vcc5_host1"vcc5v-otg-regulatorregulator-fixed g z1 default  vcc5_host2" #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemarvell,caldata-txpwrlimit-2gmarvell,caldata-txpwrlimit-5g-sub0marvell,caldata-txpwrlimit-5g-sub1marvell,caldata-txpwrlimit-5g-sub2mmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcehid-descr-addrreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type