!80(,rockchip,rk3288-evb-act8846rockchip,rk3288&7Rockchip RK3288 EVB ACT8846aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbopp-table-0operating-points-v2jbopp-126000000u| opp-216000000u | opp-312000000u| opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ| opp-1608000000u_"|preserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample  @'reset3okay:DVgydefault mmc@ff0d0000rockchip,rk3288-dw-mshcр 5Eswbiuciuciu-driveciu-sample ! @'reset 3disabledmmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample "@'reset 3disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample #@'reset3okay:Dydefaultsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW 'saradc-apb3okaybzspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,default 3disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -default  3disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .default!"#$ 3disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault% 3disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault& 3disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault' 3disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault(3okaybmserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclktxrxdefault)3okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclktxrxdefault*3okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault+3okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclktxrxdefault,3okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclk  txrxdefault-3okaydma-controller@ff250000arm,pl330arm,primecell%@-5 apb_pclkbthermal-zonesreserve-thermalDZh.cpu-thermalDdZh.tripscpu_alert0xppassiveb/cpu_alert1x$passiveb0cpu_critx_ criticalcooling-mapsmap0/0map100gpu-thermalDdZh.tripsgpu_alert0xppassiveb1gpu_critx_ criticalcooling-mapsmap01 2tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 'tsadc-apbinitdefaultsleep3435s3okayb.ethernet@ff290000rockchip,rk3288-gmac)#macirqeth_wake_irq585fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 'stmmaceth3okay36>rgmiiGinput T7d z'B@8default90usb@ff500000 generic-ehciP 5:usb3okayusb@ff520000 generic-ohciR )5:usb 3disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost; usb2-phy3okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otgotg@@ < usb2-phy 3disabledusb@ff5c0000 generic-ehci\ 5 3disableddma-controller@ff600000arm,pl330arm,primecell`@-5 apb_pclk 3disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault=3okaysyr827@40silergy,syr827&@Cvdd_cpuR Pjp>b syr828@41silergy,syr828&ACvdd_gpuR Pjp>brhym8563@51haoyu,hym8563Q&?default@xin32kact8846@5aactive-semi,act8846Z3okay>>>>A>BregulatorsREG1CVCC_DDRROjOREG2CVCC_IOR2Zj2ZbAREG3CVDD_LOGR `j`REG4CVCC_20RjbBREG5 CVCCIO_SDRw@j2ZbREG6 CVDD10_LCDRB@jB@REG7 CVCCA_CODECR2Zj2ZREG8CVCCA_TPR2Zj2ZREG9 CVCCIO_PMUR2Zj2ZREG10CVDD_10RB@jB@REG11CVCC_18Rw@jw@bREG12 CVCC18_LCDRw@jw@i2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultC 3disabledpwm@ff680000rockchip,rk3288-pwmhdefaultD5_3okayb}pwm@ff680010rockchip,rk3288-pwmhdefaultE5_ 3disabledpwm@ff680020rockchip,rk3288-pwmh defaultF5_ 3disabledpwm@ff680030rockchip,rk3288-pwmh0defaultG5_ 3disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerh bYpower-domain@9 5chgfdehilkj$"HIJKLMNOPpower-domain@11 5op"QRpower-domain@12 5"Spower-domain@13 5"TUreboot-modesyscon-reboot-mode)0RB?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~O h{default|u}B@b~external-gmac-clock fixed-clocksY@ ext_gmacb8panellg,lp079qx1-sp0vz~ h{portsportendpointblgpio-keys gpio-keysdefaultpower o?tGPIO Key Powerdvcc-host-regulatorregulator-fixed _?default Cvcc_hostvcc-phy-regulatorregulator-fixed _?defaultCvcc_phyR2Zj2Zb6vsys-regulatorregulator-fixedCvcc_sysRLK@jLK@b>sdmmc-regulatorregulator-fixed _{ defaultCvcc_sdR2Zj2ZAbvcc-lcdregulator-fixed _{defaultCvcc_lcdAbvcc-wlregulator-fixed _{ defaultCvcc_wl #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplyvp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltbrightness-levelsdefault-brightness-levelenable-gpiospwmsbacklightpower-supplyautorepeatlinux,input-typewakeup-sourcedebounce-intervalenable-active-highstartup-delay-us