d8^('^$,rockchip,rk3229-evbrockchip,rk3229!7Rockchip RK3229 Evaluation boardaliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000Z/mmc@30020000cpuscpu@f00_cpu,arm,cortex-a7kov@pscicpu@f01_cpu,arm,cortex-a7kovpscicpu@f02_cpu,arm,cortex-a7kovpscicpu@f03_cpu,arm,cortex-a7kovpsciopp-table-0,operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxopp-1296000000M?d7opp-1392000000R<opp-1464000000WB\arm-pmu,arm,cortex-a7-pmu0 LMNOpsci,arm,psci-1.0arm,psci-0.2smctimer,arm,armv7-timer*0    Nn6oscillator ,fixed-clockNn6^xin24mq+display-subsystem,rockchip,display-subsystem~ i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2sk @  i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2sk @  i2s_clki2s_hclkP txrx disabledspdif@100d0000,rockchip,rk3228-spdifk   S mclkhclk txdefault  disabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2sk@  i2s_clki2s_hclkR txrx disabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfdk,io-domains",rockchip,rk3228-io-voltage-domainokay  power-controller!,rockchip,rk3228-power-controller2power-domain@4k8power-domain@5kpower-domain@6kpower-domain@7k power-domain@8kusb2phy@760,rockchip,rk3228-usb2phyk` phyclk ^usb480m_phy0qokayFotg-port$ ;<=otg-bvalidotg-idlinestateokayEhost-port  > linestateokayGusb2phy@800,rockchip,rk3228-usb2phyk phyclk ^usb480m_phy1qokayHotg-port  D linestateokayIhost-port  E linestateokayJserial@11010000,snps,dw-apb-uartk  7Nn6MUbaudclkapb_pclkdefault )3 disabledserial@11020000,snps,dw-apb-uartk  8Nn6NVbaudclkapb_pclkdefault)3 disabledserial@11030000,snps,dw-apb-uartk  9Nn6OWbaudclkapb_pclkdefault)3okayefuse@11040000,rockchip,rk3228-efusek G pclk_efuseid@7kcpu_leakage@17ki2c@11050000,rockchip,rk3228-i2ck  $i2cLdefault disabledi2c@11060000,rockchip,rk3228-i2ck  %i2cMdefault disabledi2c@11070000,rockchip,rk3228-i2ck  &i2cNdefault  disabledi2c@11080000,rockchip,rk3228-i2ck  'i2cOdefault! disabledspi@11090000,rockchip,rk3228-spik   1ARspiclkapb_pclkdefault"#$%& disabledwatchdog@110a0000 ,rockchip,rk3228-wdtsnps,dw-wdtk   (b disabledpwm@110b0000,rockchip,rk3288-pwmk @^default' disabledpwm@110b0010,rockchip,rk3288-pwmk @^default(okayWpwm@110b0020,rockchip,rk3288-pwmk @^default)okayXpwm@110b0030,rockchip,rk3288-pwmk 0@^default* disabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timerk   + a+ pclktimerclock-controller@110e0000,rockchip,rk3228-crukK,qXHekb$u#g0,eррxhррxhpdma@110f0000,arm,pl330arm,primecellk@  apb_pclk thermal-zonescpu-thermald-tripscpu_alert0pfpassive.cpu_alert1$fpassive/cpu_crit_ fcriticalcooling-mapsmap0.0map1/0tsadc@11150000,rockchip,rk3228-tsadck  :HXtsadcapb_pclkeHuoW  tsadc-apbinitdefaultsleep01!0+AsokayX-hdmi-phy@12030000,rockchip,rk3228-hdmi-phykm+sysclkrefoclkrefpclkq ^hdmiphy_phy disabled7gpu@20000000",rockchip,rk3228-maliarm,mali-400k H gpgpmmupp0ppmmu0pp1ppmmu1 buscoreo2o~ disabledvideo-codec@20020000(,rockchip,rk3228-vpurockchip,rk3399-vpuk    vepuvdpu aclkhclk}3o2iommu@20020800,rockchip,iommuk    aclkifaceo23video-codec@20030000*,rockchip,rk3228-vdecrockchip,rk3399-vdeck    axiahbcabaccoreeu}4o2iommu@20030480,rockchip,iommuk @ @   aclkifaceo24vop@20050000,rockchip,rk3228-vopk   aclk_vopdclk_vophclk_vopodef  axiahbdclk}5o2 disabledport endpoint@0k6;iommu@20053f00,rockchip,iommuk ?   aclkifaceo2 disabled5rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rgak   !aclkhclksclko2okmn  coreaxiahbiommu@20070800,rockchip,iommuk    aclkifaceo2 disabledhdmi@200a0000,rockchip,rk3228-dw-hdmik 3  #e7l{iahbisfrcecdefault 89:o` hdmi7hdmiK, disabledportsportendpoint@0k;6mmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@   Drvbiuciuciu-driveciu-sampledefault <=> disabledmmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@   Eswbiuciuciu-driveciu-sampledefault ?@A disabledmmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshck0@  N<4`<4` Guybiuciuciu-driveciu-sampledefault BCDoS resetokayusb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2k0  otg(otg0BQ@ E usb2-phyokayusb@30080000 ,generic-ehcik0   FGusbokayusb@300a0000 ,generic-ohcik0    FGusbokayusb@300c0000 ,generic-ehcik0    HIusbokayusb@300e0000 ,generic-ohcik0   HIusbokayusb@30100000 ,generic-ehcik0  B HJusbokayusb@30120000 ,generic-ohcik0  C HJusbokayethernet@30200000,rockchip,rk3228-gmack0   macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_maco8  stmmacethK,okaye}~ K}`inputLmrgmiidefaultM vN 'B@0qos@31030080,rockchip,rk3228-qossysconk1 qos@31030100,rockchip,rk3228-qossysconk1 qos@31030180,rockchip,rk3228-qossysconk1 qos@31030200,rockchip,rk3228-qossysconk1 qos@31040000,rockchip,rk3228-qossysconk1 qos@31050000,rockchip,rk3228-qossysconk1 qos@31060000,rockchip,rk3228-qossysconk1 qos@31070000,rockchip,rk3228-qossysconk1 qos@31070080,rockchip,rk3228-qossysconk1 interrupt-controller@32010000 ,arm,gic-400 k22 2@ 2`    pinctrl,rockchip,rk3228-pinctrlK,gpio@11110000,rockchip,gpio-bankk  3@gpio@11120000,rockchip,gpio-bankk  4Agpio@11130000,rockchip,gpio-bankk  5BNgpio@11140000,rockchip,gpio-bankk  6CSpcfg-pull-up Rpcfg-pull-downQpcfg-pull-none(Ppcfg-pull-none-drv-12ma5 Osdmmcsdmmc-clkDO<sdmmc-cmdDO=sdmmc-bus4@DOOOO>sdiosdio-clkDO?sdio-cmdDO@sdio-bus4@DOOOOAemmcemmc-clkDPBemmc-cmdDPCemmc-bus8DPPPPPPPPDgmacrgmii-pinsDP PPOOOO O OPPPP PPMrmii-pinsDP PPOO OPPPPphy-pins DPPhdmihdmi-hpdDQ9hdmii2c-xfer DPP8hdmi-cecDP:i2c0i2c0-xfer DPPi2c1i2c1-xfer DPPi2c2i2c2-xfer DPP i2c3i2c3-xfer DPP!spi0spi0-clkD R"spi0-cs0DR%spi0-txD R#spi0-rxD R$spi0-cs1D R&spi1spi1-clkDRspi1-cs0DRspi1-rxDRspi1-txDRspi1-cs1DRi2s1i2s1-busDP P P P PPPPP pwm0pwm0-pinDP'pwm1pwm1-pinDP(pwm2pwm2-pinD P)pwm3pwm3-pinD P*spdifspdif-txDP tsadcotp-pinDP0otp-outDP1uart0uart0-xfer DPPuart0-ctsDPuart0-rtsDPuart1uart1-xfer D P Puart1-ctsDPuart1-rtsD Puart2uart2-xfer DRPuart21-xfer D R Puart2-ctsDPuart2-rtsDPkeyspwr-keyDRYusbhost-vbus-drvDPTmemory@60000000_memoryk`@dc-12v-regulator,regulator-fixedRdc_12vauVext_gmac ,fixed-clockNsY@ ^ext_gmacqKvcc-host-regulator,regulator-fixed SdefaultT Rvcc_hostauUvcc-phy-regulator,regulator-fixedRvcc_phyw@w@auLvcc-sys-regulator,regulator-fixedRvcc_sysauLK@LK@VUvccio-1v8-regulator,regulator-fixed Rvccio_1v8w@w@aUvccio-3v3-regulator,regulator-fixed Rvccio_3v32Z2ZaU vdd-arm-regulator,pwm-regulatorWaURvdd_arm~\auvdd-log-regulator,pwm-regulatorXaURvdd_logB@ augpio_keys ,gpio-keysdefaultYpower-keyGPIO Key Power Std #address-cells#size-cellsinterrupt-parentcompatiblemodelserial0serial1serial2spi0mmc0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsclock-namesdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supply#power-domain-cellspm_qosinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#dma-cellsarm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-modepower-domainsiommus#iommu-cellsremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeednon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplypwmspwm-supplyautorepeatlabelgpioslinux,codedebounce-intervalwakeup-source