^8X(Xd',mundoreader,bq-curie2rockchip,rk3066a 7bq Curie 2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000/spi@20070000/spi@20074000/mmc@10214000/mmc@10218000oscillator ,fixed-clockn6xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400  buscorex disabledx5gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3)video-codec@10104000,rockchip,rk3066-vpu@   vepuvdpu (aclk_vdpuhclk_vdpuaclk_vepuhclk_vepu)cache-controller@10138000,arm,pl310-cache7EQ0scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicYnQserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@ "baudclkapb_pclk@Lokaytxrxdefaultserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart` #baudclkapb_pclkAMokaytxrxdefaultqos@1012d000,rockchip,rk3066-qossyscon Qqos@1012e000,rockchip,rk3066-qossyscon Qqos@1012f000,rockchip,rk3066-qossyscon Qqos@1012f080,rockchip,rk3066-qossyscon Qqos@1012f100,rockchip,rk3066-qossyscon Qqos@1012f180,rockchip,rk3066-qossyscon Qqos@1012f200,rockchip,rk3066-qossyscon Qqos@1012f280,rockchip,rk3066-qossyscon Qusb@10180000,rockchip,rk3066-usbsnps,dwc2 otgotg@@  usb2-phy disabledusb@101c0000 ,snps,dwc2 otghost usb2-phy disabledethernet@10204000,rockchip,rk3066-emac @<  D hclkmacrefdrmii disabledmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciu rx-tx$Q/resetokay;default IU_qmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciu rx-tx$R/resetokaydefault Ummc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciu rx-tx$S/reset disablednand-controller@10500000,rockchip,rk2928-nfcP@ ahb disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode@RBRBRB RBpower-controller!,rockchip,rk3066-power-controllerQpower-domain@7POpower-domain@6 power-domain@8grf@20008000&,rockchip,rk3066-grfsysconsimple-mfd Q usbphy,rockchip,rk3066a-usb-phy disabledusb-phy@17c|QphyclkQusb-phy@188RphyclkQdma-controller@20018000,arm,pl330arm,primecell @ $ apb_pclkQdma-controller@2001c000,arm,pl330arm,primecell @ $ apb_pclk disabledi2c@2002d000,rockchip,rk3066-i2c  ( i2cP disableddefaulti2c@2002f000,rockchip,rk3066-i2c  ) Qi2cokaydefaulttps@2d-;G ,ti,tps65910regulatorsregulator@0Svcc_rtcbvvrtcregulator@1Svcc_iobvvioQregulator@2Svdd_arm '`bvvdd1Q1regulator@3Svcc_ddr '`bvvdd2regulator@5 Svcc18_cifbvvdig1regulator@6Svdd_11bvvdig2regulator@7Svcc_25bvvpllregulator@8Svcc_18bvvdacregulator@9 Svcc25_hdmib vvaux1regulator@10Svcca_33b vvaux2regulator@11Svcc_tpb vvaux33regulator@12 Svcc28_cifb vvmmcregulator@4vvdd3regulator@13 vvbbpwm@20030000,rockchip,rk2928-pwm F disableddefaultpwm@20030010,rockchip,rk2928-pwm F disableddefault watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  G disableddefault!pwm@20050030,rockchip,rk2928-pwm 0Gokaydefault"Q?i2c@20056000,rockchip,rk3066-i2c ` * Ri2c disableddefault#i2c@2005a000,rockchip,rk3066-i2c  + Si2c disableddefault$i2c@2005e000,rockchip,rk3066-i2c  4 Ti2c disableddefault%serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @ $baudclkapb_pclkBNokay  txrxdefault&serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart  %baudclkapb_pclkCOokay  txrxdefault'saradc@2006c000,rockchip,saradc  GJsaradcapb_pclkW /saradc-apb disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk &  txrx disableddefault()*+spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @ txrx disableddefault,-./dma-controller@20078000,arm,pl330arm,primecell @ $ apb_pclkQ cpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a908@ Oa* s* 'g8&@41cpu@1cpu,arm,cortex-a9041display-subsystem,rockchip,display-subsystem?23sram@10080000 ,mmio-sram Esmp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3066-vop  aclk_vopdclk_vophclk_vop)def /axiahbdclk disabledportQ2endpoint@0L4Q8vop@1010e000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop)ghi /axiahbdclk disabledportQ3endpoint@0L5Q9hdmi@10116000,rockchip,rk3066-hdmi`  @hclkdefault67)  disabledportsport@0endpoint@0L8Q4endpoint@1L9Q5port@1i2s@10118000,rockchip,rk3066-i2s  default:Ki2s_clki2s_hclktxrx\w disabledi2s@1011a000,rockchip,rk3066-i2s   default;Li2s_clki2s_hclktxrx\w disabledi2s@1011c000,rockchip,rk3066-i2s  default<Mi2s_clki2s_hclk  txrx\w disabledclock-controller@20000000,rockchip,rk3066a-cru  @^_ ׄ#gрxhрxhQtimer@2000e000,snps,dw-apb-timer  .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer  ,TB timerpclktimer@2003a000,snps,dw-apb-timer  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk \ /saradc-apb disabledpinctrl,rockchip,rk3066a-pinctrl Egpio@20034000,rockchip,gpio-bank @ 6UYngpio@2003c000,rockchip,gpio-bank  7VYngpio@2003e000,rockchip,gpio-bank  8WYngpio@20080000,rockchip,gpio-bank  9XYnQ@gpio@20084000,rockchip,gpio-bank @ :YYnQAgpio@2000a000,rockchip,gpio-bank  <ZYnQpcfg-pull-defaultQ>pcfg-pull-noneQ=emacemac-xfer========emac-mdio ==emmcemmc-clk>emmc-cmd >emmc-rst >hdmihdmi-hpd>Q7hdmii2c-xfer ==Q6i2c0i2c0-xfer ==Qi2c1i2c1-xfer ==Qi2c2i2c2-xfer ==Q#i2c3i2c3-xfer ==Q$i2c4i2c4-xfer ==Q%pwm0pwm0-out=Qpwm1pwm1-out=Q pwm2pwm2-out=Q!pwm3pwm3-out=Q"spi0spi0-clk>Q(spi0-cs0>Q+spi0-tx>Q)spi0-rx>Q*spi0-cs1>spi1spi1-clk>Q,spi1-cs0>Q/spi1-rx>Q.spi1-tx>Q-spi1-cs1>uart0uart0-xfer >>Quart0-cts>uart0-rts>uart1uart1-xfer >>Quart1-cts>uart1-rts>uart2uart2-xfer > >Q&uart3uart3-xfer >>Q'uart3-cts>uart3-rts>sd0sd0-clk>Q sd0-cmd >Q sd0-cd>Q sd0-wp>sd0-bus-width1 >sd0-bus-width4@ > > > >Qsd1sd1-clk>Qsd1-cmd>Qsd1-cd>sd1-wp>sd1-bus-width1>sd1-bus-width4@>>>>Qi2s0i2s0-bus>> > > > > >>>Q:i2s1i2s1-bus`>>>>>>Q;i2s2i2s2-bus`>>>>>>Q<memory@60000000memory`@vdd-log,pwm-regulator ?Svdd_logOObB@dO*okayfixed-regulator,regulator-fixed Ssdmmc-supply-- @%Qgpio-keys ,gpio-keys0power ;AtLGPIO Key PowerRcqdvolume-down ;AArLGPIO Key Vol-Rqd #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0mmc1clock-frequency#clock-cellsclock-output-namesregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelphandleinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modefifo-depthreset-namesmax-frequencyvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsrangesremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supplyautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-interval