Ð þí2×8/(».ä1Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1'!qcom,ipq4019-ap-dk01.1-c1qcom,ipq4019,reserved-memory=smem@87e00000D‡àHtz@87e80000D‡èHaliasesO/soc/spi@78b5000T/soc/spi@78b6000Y/soc/i2c@78b7000^/soc/i2c@78b8000c/soc/serial@78af000cpuscpu@0kcpu!arm,cortex-a7wqcom,kpss-acc-v2…–ŸD¨ ¯¿èÍcpu@1kcpu!arm,cortex-a7wqcom,kpss-acc-v2…–ŸD¨ ¯¿èÍcpu@2kcpu!arm,cortex-a7wqcom,kpss-acc-v2…– Ÿ D¨ ¯¿èÍcpu@3kcpu!arm,cortex-a7wqcom,kpss-acc-v2…– Ÿ D¨ ¯¿èÍl2-cache!cache០íopp_table0!operating-points-v2õíopp-48000000Ülèopp-200000000 ëÂèopp-500000000Íeèopp-716000000*­KèmemorykmemoryDpmu!arm,cortex-a7-pmu clockssleep_clk !fixed-clock¯}#gcc_sleep_clk_src6íxo !fixed-clock¯Ül6firmwarescm!qcom,scm-ipq4019timer!arm,armv7-timer0¯ÜlCsoc= !simple-businterrupt-controller@b000000!qcom,msm-qgic2MbD  íclock-controller@1800000!qcom,gcc-ipq40196s‡D€írng@22000 !qcom,prngD @¨+”core okaypinctrl@1000000!qcom,ipq4019-pinctrlD0§·dÃMb Ðíserial_pinmuxímuxÏgpio60gpio61 Ôblsp_uart0Ýspi_0_pinmuxípinmux Ôblsp_spi0Ïgpio55gpio56gpio57pinmux_csÔgpioÏgpio54pinconfÏgpio55gpio56gpio57ê Ýpinconf_csÏgpio54êÝùregulator@1948000!qcom,vqmmc-ipq4019-regulatorD”€vqmmcã`,-ÆÀD  disabledsdhci@7824900!qcom,sdhci-msm-v4D‚I‚@{ŠXhc_irqpwr_irqh¨/.”coreifacexo  disableddma@7884000!qcom,bam-v1.7.0Dˆ@0 bam_clkr} okayíspi@78b5000!qcom,spi-qup-v2.2.1D‹P _¨ ”coreiface…Šrxtx okay”ždefault ¬6mx25l25635e@0D !mx25l25635eµn6spi@78b6000!qcom,spi-qup-v2.2.1D‹` `¨ ”coreiface…Šrxtx  disabledi2c@78b7000!qcom,i2c-qup-v2.2.1D‹p a¨ ”ifacecore… Šrxtx  disabledi2c@78b8000!qcom,i2c-qup-v2.2.1D‹€ b¨ ”ifacecore…  Šrxtx  disableddma@8e04000!qcom,bam-v1.7.0Dà@ Ϩ!”bam_clkr}Ç okayícrypto@8e3a000!qcom,crypto-v5.1Dã `¨!"#”ifacebuscore…Šrxtx okayclock-controller@b088000!qcom,kpss-acc-v2D € €íclock-controller@b098000!qcom,kpss-acc-v2D € €íclock-controller@b0a8000!qcom,kpss-acc-v2D € €í clock-controller@b0b8000!qcom,kpss-acc-v2D € €í regulator@b089000 !qcom,saw2D  àíregulator@b099000 !qcom,saw2D  àíregulator@b0a9000 !qcom,saw2D  àí regulator@b0b9000 !qcom,saw2D  àí regulator@b012000 !qcom,saw2D  àí serial@78af000%!qcom,msm-uartdm-v1.4qcom,msm-uartdmDŠð k okay¨ ”coreiface…Šrxtx”ždefaultserial@78b0000%!qcom,msm-uartdm-v1.4qcom,msm-uartdmD‹ l  disabled¨ ”coreiface…Šrxtxwatchdog@b017000$!qcom,kpss-wdtqcom,kpss-wdt-ipq4019D p@¨ê  okayrestart@4ab000 !qcom,psholdDJ°pci@40000000!qcom,pcie-ipq4019snps,dw-pcie D@@ ¨ @ödbielbiparfconfigkpciÿ0=@ @ ‚@0@0Ð Xmsib%€8Ž‘¨'()”auxmaster_busslave_bus`FXMaxi_maxi_spipeaxi_m_vmidaxi_s_xpuparfphyaxi_m_stickypipe_stickypwrahbphy_ahb  disableddma@7984000!qcom,bam-v1.7.0D˜@  e¨-”bam_clkr}  disabledínand-controller@79b0000!qcom,ipq4019-nandD›¨-, ”coreaon… Štxrxcmd  disablednand@0DYk~wifi@a000000!qcom,ipq4019-wifiD 0F\Mwifi_cpu_initwifi_radio_srifwifi_radio_warmwifi_radio_coldwifi_core_warmwifi_core_cold¨;<=*”wifi_wcss_cmdwifi_wcss_refwifi_wcss_rtcÌ !"#$%&'()*+,-./¨]Xmsi0msi1msi2msi3msi4msi5msi6msi7msi8msi9msi10msi11msi12msi13msi14msi15legacy okaywifi@a800000!qcom,ipq4019-wifiD € 0F   \Mwifi_cpu_initwifi_radio_srifwifi_radio_warmwifi_radio_coldwifi_core_warmwifi_core_cold¨>?@*”wifi_wcss_cmdwifi_wcss_refwifi_wcss_rtcÌ0123456789:;<=>?©]Xmsi0msi1msi2msi3msi4msi5msi6msi7msi8msi9msi10msi11msi12msi13msi14msi15legacy okaymdio@90000!qcom,ipq4019-mdioD d  disabledethernet-phy@0Dethernet-phy@1Dethernet-phy@2Dethernet-phy@3Dethernet-phy@4Dssphy@9a000!qcom,usb-ss-ipq4019-phyD   öphy_baseF Mpor_rst  disabledíhsphy@a6000!qcom,usb-hs-ipq4019-phyD `@ öphy_baseF Mpor_rstsrif_rst  disabledíusb3@8af8800!qcom,ipq4019-dwc3qcom,dwc3D¯ˆ¨89:”mastersleepmock_utmi=  disableddwc3@8a00000 !snps,dwc3D € „˜usb2-phyusb3-phy§hosthsphy@a8000!qcom,usb-hs-ipq4019-phyD €@ öphy_baseFMpor_rstsrif_rst  disabledíusb2@60f8800!qcom,ipq4019-dwc3qcom,dwc3Dˆ¨567”mastersleepmock_utmi=  disableddwc3@6000000 !snps,dwc3D€ ˆ˜ usb2-phy§hostchosen¯serial0:115200n8 #address-cells#size-cellsmodelcompatibleinterrupt-parentrangesregno-mapspi0spi1i2c0i2c1serial0device_typeenable-methodnext-level-cacheqcom,accqcom,sawclocksclock-frequencyclock-latencyoperating-points-v2cache-levelphandleopp-sharedopp-hzclock-latency-nsinterruptsclock-output-names#clock-cellsalways-oninterrupt-controller#interrupt-cells#power-domain-cells#reset-cellsclock-namesstatusgpio-controllergpio-ranges#gpio-cellspinsfunctionbias-disabledrive-strengthoutput-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-oninterrupt-namesbus-width#dma-cellsqcom,eedmasdma-namespinctrl-0pinctrl-namescs-gpiosspi-max-frequencyqcom,controlled-remotelyregulatortimeout-secreg-nameslinux,pci-domainbus-rangenum-lanesinterrupt-map-maskinterrupt-mapresetsreset-namesnand-ecc-strengthnand-ecc-step-sizenand-bus-width#phy-cellsphysphy-namesdr_modestdout-path