v8n$(mElement14 Warp i.MX7 Board!element14,imx7s-warpfsl,imx7schosenaliases ,/soc/bus@30000000/gpio@30200000 2/soc/bus@30000000/gpio@30210000 8/soc/bus@30000000/gpio@30220000 >/soc/bus@30000000/gpio@30230000 D/soc/bus@30000000/gpio@30240000 J/soc/bus@30000000/gpio@30250000 P/soc/bus@30000000/gpio@30260000V/soc/bus@30800000/i2c@30a20000[/soc/bus@30800000/i2c@30a30000`/soc/bus@30800000/i2c@30a40000e/soc/bus@30800000/i2c@30a50000j/soc/bus@30800000/mmc@30b40000o/soc/bus@30800000/mmc@30b50000t/soc/bus@30800000/mmc@30b600004y/soc/bus@30800000/spba-bus@30800000/serial@308600004/soc/bus@30800000/spba-bus@30800000/serial@308900004/soc/bus@30800000/spba-bus@30800000/serial@30880000"/soc/bus@30800000/serial@30a60000"/soc/bus@30800000/serial@30a70000"/soc/bus@30800000/serial@30a80000"/soc/bus@30800000/serial@30a900001/soc/bus@30800000/spba-bus@30800000/spi@308200001/soc/bus@30800000/spba-bus@30800000/spi@308300001/soc/bus@30800000/spba-bus@30800000/spi@30840000/soc/bus@30400000/spi@30630000/soc/bus@30800000/usb@30b10000/soc/bus@30800000/usb@30b30000cpusidle-statespscicpu-sleep-wait!arm,idle-stated2%6cpu@0!arm,cortex-a7>cpuJN/4^lls speed_grade6opp-table!operating-points-v26opp-792000000/4B@Iclock-cki !fixed-clockNckil6clock-osc !fixed-clockNn6osc6usbphynop1!usb-nop-xceivl %main_clk168usbphynop3!usb-nop-xceivln %main_clk16;pmu!arm,cortex-a7-pmu< M\Xreplicator !arm,coresight-static-replicatorout-portsport@0Jendpointk6port@1Jendpointk6in-portsportendpointk 6timer!arm,armv7-timer{< 0M   soc !simple-bus<funnel@30041000+!arm,coresight-dynamic-funnelarm,primecellJ0lJ %apb_pclkin-portsportendpointk 6 out-portsportendpointk 6etm@3007c000"!arm,coresight-etm3xarm,primecellJ0lJ %apb_pclkout-portsportendpointk 6 funnel@30083000+!arm,coresight-dynamic-funnelarm,primecellJ00lJ %apb_pclkin-portsport@0Jendpointk6 port@1Jendpointout-portsportendpointk6etf@30084000 !arm,coresight-tmcarm,primecellJ0@lJ %apb_pclkin-portsportendpointk6out-portsportendpointk6 etr@30086000 !arm,coresight-tmcarm,primecellJ0`lJ %apb_pclkin-portsportendpointk6tpiu@30087000!!arm,coresight-tpiuarm,primecellJ0plJ %apb_pclkin-portsportendpointk6interrupt-controller@31001000!arm,cortex-a7-gic M <  J11 1@ 1` 6 bus@30000000!fsl,aips-bussimple-busJ0@gpio@30200000!fsl,imx7d-gpiofsl,imx35-gpioJ0 M@A 6.gpio@30210000!fsl,imx7d-gpiofsl,imx35-gpioJ0!MBC gpio@30220000!fsl,imx7d-gpiofsl,imx35-gpioJ0"MDE-gpio@30230000!fsl,imx7d-gpiofsl,imx35-gpioJ0#MFGJgpio@30240000!fsl,imx7d-gpiofsl,imx35-gpioJ0$MHIb6Egpio@30250000!fsl,imx7d-gpiofsl,imx35-gpioJ0%MJKtgpio@30260000!fsl,imx7d-gpiofsl,imx35-gpioJ0&MLM6Dwatchdog@30280000!fsl,imx7d-wdtfsl,imx21-wdtJ0( MNlBdefault%okaywatchdog@30290000!fsl,imx7d-wdtfsl,imx21-wdtJ0) MOl %disabledwatchdog@302a0000!fsl,imx7d-wdtfsl,imx21-wdtJ0* M l %disabledwatchdog@302b0000!fsl,imx7d-wdtfsl,imx21-wdtJ0+ Mml %disablediomuxc-lpsr@302c0000!fsl,imx7d-iomuxc-lpsrJ0,,6wdoggrp:0t6timer@302d0000!fsl,imx7d-gptfsl,imx6sx-gptJ0- M7l..%ipgpertimer@302e0000!fsl,imx7d-gptfsl,imx6sx-gptJ0. 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#address-cells#size-cellsmodelcompatiblegpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2i2c3mmc0mmc1mmc2serial0serial1serial2serial3serial4serial5serial6spi0spi1spi2spi3usb0usb1entry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usphandledevice_typeregclock-frequencyclock-latencyclockscpu-idle-statesoperating-points-v2#cooling-cellsnvmem-cellsnvmem-cell-namesopp-sharedopp-hzopp-microvoltclock-latency-nsopp-supported-hw#clock-cellsclock-output-namesclock-names#phy-cellsinterrupt-parentinterruptsinterrupt-affinityremote-endpointarm,cpu-registers-not-fw-configuredrangescpu#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsgpio-rangespinctrl-namespinctrl-0fsl,ext-reset-outputstatusfsl,input-selfsl,pins#mux-control-cellsmux-reg-masksmux-controlsregulator-nameregulator-min-microvoltregulator-max-microvoltanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitfsl,tempmonregmaplinux,keycodewakeup-sourceassigned-clocksassigned-clock-rates#reset-cells#power-domain-cellspower-supply#io-channel-cells#pwm-cellspower-domainsphy-supplyresetsdata-lanesassigned-clock-parentsuart-has-rtscts#sound-dai-cellsdma-namesdmasfsl,stop-moderegulator-boot-onregulator-always-onregulator-ramp-delayreset-gpiosDOVDD-supplyDVDD-supplyAVDD-supplyclock-lanesVDDA-supplyVDDIO-supplyVDDD-supplyfsl,dte-mode#mbox-cellsfsl,mu-side-bfsl,usbphyfsl,usbmiscphy-clkgate-delay-usdr_modephy_type#index-cellsbus-widthkeep-power-in-suspendno-1-8-vnon-removablevmmc-supplypinctrl-1pinctrl-2fsl,tuning-stepreg-names#dma-cellsfsl,sdma-ram-script-nameinterrupt-namesfsl,num-tx-queuesfsl,num-rx-queuesdma-channelsautorepeatlabellinux,codeenable-active-highgpiostartup-delay-ussimple-audio-card,namesimple-audio-card,formatsimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersound-dai