Q8I(tI\#itead,sonoff-ihostrockchip,rv1109&7Sonoff iHost 2Galiases=/i2c@ff3f0000B/i2c@ff400000G/serial@ff560000O/serial@ff410000W/serial@ff570000_/serial@ff580000g/serial@ff590000o/serial@ff5a0000w/ethernet@ffc40000/mmc@ffc50000cpuscpu@f00cpuarm,cortex-a7pscicpu@f01cpuarm,cortex-a7psciarm-pmuarm,cortex-a7-pmu{|psci arm,psci-1.0smctimerarm,armv7-timer0   n6display_subsystemrockchip,display-subsystemoscillator fixed-clockn6xin24m syscon@fe000000&rockchip,rv1126-grfsysconsimple-mfdsyscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfdio-domains&rockchip,rv1126-pmu-io-voltage-domainokay'5 C Q _ m {  qos@fe860000rockchip,rv1126-qossyscon  qos@fe860080rockchip,rv1126-qossyscon  qos@fe860200rockchip,rv1126-qossyscon qos@fe86c000rockchip,rv1126-qossyscon qos@fe8a0000rockchip,rv1126-qossyscon qos@fe8a0080rockchip,rv1126-qossyscon qos@fe8a0100rockchip,rv1126-qossyscon qos@fe8a0180rockchip,rv1126-qossyscon interrupt-controller@feff0000 arm,gic-400  @ `   power-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfd>power-controller!rockchip,rv1126-power-controller.power-domain@158ruv  power-domain@16opower-domain@10 PZ[i2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2c?  ! i2cpclkdefaultokaypmic@20rockchip,rk809 & rk808-clkout1rk808-clkout2default *8DP\htLregulatorsDCDC_REG1 vdd_npu_vepu ~ qregulator-state-mem5DCDC_REG2vdd_arm p qregulator-state-mem5DCDC_REG3vcc_ddrregulator-state-memNDCDC_REG4 vcc3v3_sys2Z2Zregulator-state-memNf2ZDCDC_REG5 vcc_buck5!!regulator-state-memNf!LDO_REG1vcc_0v8 5 5regulator-state-mem5LDO_REG2 vcc1v8_pmuw@w@regulator-state-memNfw@LDO_REG3 vcc0v8_pmu 5 5regulator-state-memNf 5LDO_REG4vcc_1v8w@w@ regulator-state-memNfw@LDO_REG5 vcc_dovddw@w@ regulator-state-mem5LDO_REG6 vcc_dvddOOregulator-state-mem5LDO_REG7 vcc_avdd**regulator-state-mem5LDO_REG8 vccio_sdw@2Z regulator-state-mem5LDO_REG9 vcc3v3_sd2Z2Zregulator-state-mem5SWITCH_REG1vcc_5v0SWITCH_REG2vcc_3v33i2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2c@  " i2cpclkdefaultokayrtc@51 nxp,pcf8563Q&xin32kserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uartA n6  baudclkapb_pclktxrxdefault disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwmC  pwmpclk#default disabledclock-controller@ff480000rockchip,rv1126-pmucruHclock-controller@ff490000rockchip,rv1126-cruI xin24mdma-controller@ff4e0000arm,pl330arm,primecellN@ apb_pclkpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwmU0 pwmpclk'!default disabledserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uartV n6baudclkapb_pclktxrxdefault "#$okaybluetoothrealtek,rtl8723ds-bt % % %!default &'(serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uartW n6baudclkapb_pclk txrxdefault)okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uartX n6baudclkapb_pclk  txrxdefault*okayserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uartY n6baudclkapb_pclk  txrxdefault+okayserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uartZ n6 baudclkapb_pclktxrxdefault, disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc^ (+, saradcapb_pclk=; Dsaradc-apbokayP timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timerf   - pclktimervop@ffb00000rockchip,rv1126-vop  ;aclk_vopdclk_vophclk_vop Daxiahbdclk=\-c.  disabledportendpoint@0endpoint@1iommu@ffb00f00rockchip,iommu ; aclkifaceqc.  disabled-ethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a@_`~macirqeth_wake_irq@~Tstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_ref= Dstmmaceth/01okay}~|}output'22rmii;3default4567mdiosnps,dwmac-mdioethernet-phy@0ethernet-phy-ieee802.3-c22default8FWPg' y92stmmac-axi-config/rx-queues-config0queue0tx-queues-config1queue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ N rstbiuciuciu-driveciu-sample c.okaydefault:;<=-ZK3W mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ L lmnbiuciuciu-driveciu-sample okaydudefault>?@A-ZW mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ M opqbiuciuciu-driveciu-samplec.okaydBdefault CDE-ZKW spi@ffc90000 rockchip,sfc@ PvĴclk_sfchclk_sfcvc. disabledpinctrlrockchip,rv1126-pinctrlgpio@ff460000rockchip,gpio-bankF "&gpio@ff620000rockchip,gpio-bankb #(%gpio@ff630000rockchip,gpio-bankc $)9gpio@ff640000rockchip,gpio-bankd %*gpio@ff650000rockchip,gpio-banke & +pcfg-pull-up Ipcfg-pull-downHpcfg-pull-none)Fpcfg-pull-none-drv-level-3)6Kpcfg-pull-up-drv-level-2 6Gpcfg-pull-none-drv-level-0-smt)6EJclk_out_ethernetemmcemmc-rstnoutZF=emmc-bus8ZGGGGGGGG:emmc-clkZG<emmc-cmdZG;fspii2c0i2c0-xfer Z J Ji2c2i2c2-xfer ZJJpwm2pwm2m0-pinsZFpwm11pwm11m0-pinsZF!rgmiirgmiim1-miim ZFF4rgmiim1-rxerZF5rgmiim1-bus2`Z FF FKKK6rgmiim1-mclkinoutZF7sdmmc0sdmmc0-bus4@ZGGGG@sdmmc0-clkZG>sdmmc0-cmdZ G?sdmmc0-detZFAsdmmc1sdmmc1-bus4@Z G GGGEsdmmc1-clkZ GCsdmmc1-cmdZ GDuart0uart0-xfer ZII"uart0-ctsnZF#uart0-rtsnZF$uart1uart1m0-xfer ZIIuart2uart2m1-xfer ZII)uart3uart3m2-xfer ZII*uart4uart4m2-xfer ZII+uart5uart5m0-xfer ZII,etherneteth-phy-rstZH8btbt-enableZF&bt-wake-devZF'bt-wake-hostZF(pmicpmic-int-lZ Iwifiwifi-enable-hZFMchosenhserial2:1500000n8regulator-vcc5v0-sysregulator-fixed vcc5v0_sysLK@LK@pwrseq-sdiommc-pwrseq-simpleL ext_clockdefaultM y%B #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2serial0serial1serial2serial3serial4serial5ethernet0mmc0device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosmax-speed#io-channel-cellsresetsreset-namesvref-supplyiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplyreset-active-lowreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthcap-mmc-highspeedmmc-hs200-1_8vnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-path