8( L7radxa,rockpi-n8vamrs,rk3288-vmarc-somrockchip,rk3288&7Radxa ROCK Pi N8aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]@krrcpu@501#cpuarm,cortex-a12/3:N]@krrcpu@502#cpuarm,cortex-a12/3:N]@krrcpu@503#cpuarm,cortex-a12/3:N]@krropp-table-0operating-points-v2opp-126000000 opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ka  &pclktimerdisplay-subsystemrockchip,display-subsystem2 mmc@ff0c0000rockchip,rk3288-dw-mshc8р kDrv&biuciuciu-driveciu-sampleF / @3Qreset]okaydn default mmc@ff0d0000rockchip,rk3288-dw-mshc8р kEsw&biuciuciu-driveciu-sampleF !/ @3Qreset]okayddefault mmc@ff0e0000rockchip,rk3288-dw-mshc8р kFtx&biuciuciu-driveciu-sampleF "/@3Qreset ]disabledmmc@ff0f0000rockchip,rk3288-dw-mshc8р kGuy&biuciuciu-driveciu-sampleF #/@3Qreset]okaydndefault saradc@ff100000rockchip,saradc/ $kI[&saradcapb_pclk3W Qsaradc-apb ]disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR&spiclkapb_pclk)  .txrx ,default/ ]disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS&spiclkapb_pclk) .txrx -default !"#/ ]disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT&spiclkapb_pclk).txrx .default$%&'/ ]disabledi2c@ff140000rockchip,rk3288-i2c/ >&i2ckMdefault(]okayrtc@51haoyu,hym8563/Q&)hym8563default*i2c@ff150000rockchip,rk3288-i2c/ ?&i2ckOdefault+ ]disabledi2c@ff160000rockchip,rk3288-i2c/ @&i2ckPdefault, ]disabledi2c@ff170000rockchip,rk3288-i2c/ A&i2ckQdefault-]okayrserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 78BkMU&baudclkapb_pclk).txrxdefault./]okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 88BkNV&baudclkapb_pclk).txrxdefault0 ]disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 98BkOW&baudclkapb_pclkdefault1]okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :8BkPX&baudclkapb_pclk).txrxdefault2 ]disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;8BkQY&baudclkapb_pclk)  .txrxdefault3 ]disableddma-controller@ff250000arm,pl330arm,primecell/%@OZuk &apb_pclkthermal-zonesreserve-thermal4cpu-thermald4tripscpu_alert0p*passive5cpu_alert1$*passive6cpu_crit_ *criticalcooling-mapsmap050map160gpu-thermald4tripsgpu_alert0p*passive7gpu_crit_ *criticalcooling-mapsmap07 8tsadc@ff280000rockchip,rk3288-tsadc/( %kHZ&tsadcapb_pclk3 Qtsadc-apbinitdefaultsleep9:9;"s ]disabled4ethernet@ff290000rockchip,rk3288-gmac/)9macirqeth_wake_irq;8kfgc]M&stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B Qstmmaceth]okayI<`inputmrgmiidefault=v 'P( >usb@ff500000 generic-ehci/P k?usb]okayusb@ff520000 generic-ohci/R )k?usb]okayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T k&otghost@ usb2-phy]okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X k&otgotg -@@ A usb2-phy]okayusb@ff5c0000 generic-ehci/\ k ]disableddma-controller@ff600000arm,pl330arm,primecell/`@OZuk &apb_pclk ]disabledi2c@ff650000rockchip,rk3288-i2c/e <&i2ckLdefaultB]okaypmic@1brockchip,rk808/&CdefaultDE<]rk808-clkout1rk808-clkout2kFwFFFFFFFregulatorsDCDC_REG1vdd_arm"4 qL\regulator-state-memdDCDC_REG2vdd_gpu"4 PL}pregulator-state-memdDCDC_REG3vcc_ddr"regulator-state-memDCDC_REG4vcc_io"42ZL2Zregulator-state-mem2ZLDO_REG1vcc_tp"42ZL2Zregulator-state-memdLDO_REG2 vcca_codec"42ZL2Zregulator-state-mem2ZLDO_REG3vdd_10"4B@LB@regulator-state-memB@LDO_REG4vcc_wl"4w@Lw@[regulator-state-memLDO_REG5 vccio_sd"4w@L2Z regulator-state-mem2ZLDO_REG6 vdd10_lcd"4B@LB@regulator-state-memdLDO_REG7vcc_18"4w@Lw@Zregulator-state-memw@LDO_REG8 vcc18_lcd"4w@Lw@regulator-state-memdSWITCH_REG1vcc_sd"regulator-state-memdSWITCH_REG2vcc_lcd"regulator-state-memdi2c@ff660000rockchip,rk3288-i2c/f =&i2ckNdefaultG ]disabledpwm@ff680000rockchip,rk3288-pwm/hdefaultHk_]okaypwm@ff680010rockchip,rk3288-pwm/hdefaultIk_ ]disabledpwm@ff680020rockchip,rk3288-pwm/h defaultJk_]okaypwm@ff680030rockchip,rk3288-pwm/h0defaultKk_ ]disabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/spower-controller!rockchip,rk3288-power-controllerhI _power-domain@9/ kchgfdehilkj$LMNOPQRSTpower-domain@11/ kopUVpower-domain@12/ kWpower-domain@13/ kXYreboot-modesyscon-reboot-modeRBRB RB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/vk &xin24m;)Hjk$6#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w;edp-phyrockchip,rk3288-dp-phykh&24mK ]disabledoio-domains"rockchip,rk3288-io-voltage-domain]okayV`nZ~ [usbphyrockchip,rk3288-usb-phy]okayusb-phy@320K/ k]&phyclk3 Qphy-resetAusb-phy@334K/4k^&phyclk3 Qphy-reset?usb-phy@348K/Hk_&phyclk3 Qphy-reset@watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/kp O ]disabledsound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/kT &mclkhclk)\.tx 6default]; ]disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ 5kR&i2s_clki2s_hclk)\\.txrxdefault^ ]disabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 k}&aclkhclksclkapb_pclk3 Qcrypto-rstiommu@ff900800rockchip,iommu/@ k &aclkiface ]disablediommu@ff914000rockchip,iommu /@P k &aclkiface ]disabledrga@ff920000rockchip,rk3288-rga/ kj&aclkhclksclk_ 3ilm Qcoreaxiahbvop@ff930000rockchip,rk3288-vop / k&aclk_vopdclk_vophclk_vop_ 3def Qaxiahbdclk"`]okayport endpoint@0/)atendpoint@1/)bpendpoint@2/)cjendpoint@3/)dmiommu@ff930300rockchip,iommu/ k &aclkiface_ ]okay`vop@ff940000rockchip,rk3288-vop / k&aclk_vopdclk_vophclk_vop_ 3 Qaxiahbdclk"e]okayport endpoint@0/)fuendpoint@1/)gqendpoint@2/)hkendpoint@3/)iniommu@ff940300rockchip,iommu/ k &aclkiface_ ]okayedsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ k~d &refpclk_ ; ]disabledportsport@0/endpoint@0/)jcendpoint@1/)khport@1/lvds@ff96c000rockchip,rk3288-lvds/@kg &pclk_lvdslcdcl_ ; ]disabledportsport@0/endpoint@0/)mdendpoint@1/)niport@1/dp@ff970000rockchip,rk3288-dp/@ bkic&dppclkodp_ 3oQdp; ]disabledportsport@0/endpoint@0/)pbendpoint@1/)qgport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/B gkhmn&iahbisfrcec_ ;]okay9rdefaultsportsport@0/endpoint@0/)taendpoint@1/)ufport@1/video-codec@ff9a0000rockchip,rk3288-vpu/   9vepuvdpuk &aclkhclk"v_ iommu@ff9a0800rockchip,iommu/ k &aclkiface_ viommu@ff9c0440rockchip,iommu /@@@ ok &aclkiface ]disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/$ 9jobmmugpuk:wN_  ]disabled8opp-table-1operating-points-v2wopp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon/ Xqos@ffaa0080rockchip,rk3288-qossyscon/ Yqos@ffad0000rockchip,rk3288-qossyscon/ Mqos@ffad0100rockchip,rk3288-qossyscon/ Nqos@ffad0180rockchip,rk3288-qossyscon/ Oqos@ffad0400rockchip,rk3288-qossyscon/ Pqos@ffad0480rockchip,rk3288-qossyscon/ Qqos@ffad0500rockchip,rk3288-qossyscon/ Lqos@ffad0800rockchip,rk3288-qossyscon/ Rqos@ffad0880rockchip,rk3288-qossyscon/ Sqos@ffad0900rockchip,rk3288-qossyscon/ Tqos@ffae0000rockchip,rk3288-qossyscon/ Wqos@ffaf0000rockchip,rk3288-qossyscon/ Uqos@ffaf0080rockchip,rk3288-qossyscon/ Vdma-controller@ffb20000arm,pl330arm,primecell/@OZuk &apb_pclk\efuse@ffb40000rockchip,rk3288-efuse/ kq &pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400EZ@/ @ `   pinctrlrockchip,rk3288-pinctrl;gpio@ff750000rockchip,gpio-bank/u Qk@k{EZCgpio@ff780000rockchip,gpio-bank/x RkAk{EZgpio@ff790000rockchip,gpio-bank/y SkBk{EZgpio@ff7a0000rockchip,gpio-bank/z TkCk{EZgpio@ff7b0000rockchip,gpio-bank/{ UkDk{EZ>gpio@ff7c0000rockchip,gpio-bank/| VkEk{EZ)gpio@ff7d0000rockchip,gpio-bank/} WkFk{EZgpio@ff7e0000rockchip,gpio-bank/~ XkGk{EZgpio@ff7f0000rockchip,gpio-bank/ YkHk{EZhdmihdmi-cec-c0xshdmi-cec-c7xhdmi-ddc xxhdmi-ddc-unwedge yxpcfg-output-lowypcfg-pull-upzpcfg-pull-down{pcfg-pull-nonexpcfg-pull-none-12ma ~suspendglobal-pwroffxEddrio-pwroffxddr0-retentionzddr1-retentionzedpedp-hpd {i2c0i2c0-xfer xxBi2c1i2c1-xfer xx(i2c2i2c2-xfer  x xGi2c3i2c3-xfer xx+i2c4i2c4-xfer xx,i2c5i2c5-xfer xx-i2s0i2s0-bus`xxxxxx^lcdclcdc-ctl@xxxxlsdmmcsdmmc-clk| sdmmc-cmd}sdmmc-cdzsdmmc-bus1zsdmmc-bus4@}}}}sdio0sdio0-bus1zsdio0-bus4@zzzzsdio0-cmdzsdio0-clkxsdio0-cdzsdio0-wpzsdio0-pwrzsdio0-bkpwrzsdio0-intzsdio1sdio1-bus1zsdio1-bus4@zzzzsdio1-cdzsdio1-wpzsdio1-bkpwrzsdio1-intzsdio1-cmdzsdio1-clkxsdio1-pwr zemmcemmc-clkxemmc-cmdzemmc-pwr zemmc-bus1zemmc-bus4@zzzzemmc-bus8zzzzzzzzspi0spi0-clk zspi0-cs0 zspi0-txzspi0-rxzspi0-cs1zspi1spi1-clk z spi1-cs0 z#spi1-rxz"spi1-txz!spi2spi2-cs1zspi2-clkz$spi2-cs0z'spi2-rxz&spi2-tx z%uart0uart0-xfer zx.uart0-ctsz/uart0-rtsxuart1uart1-xfer z x0uart1-cts zuart1-rts xuart2uart2-xfer zx1uart3uart3-xfer zx2uart3-cts zuart3-rts xuart4uart4-xfer zx3uart4-cts zuart4-rts xtsadcotp-pin x9otp-out x:pwm0pwm0-pinxHpwm1pwm1-pinxIpwm2pwm2-pinxJpwm3pwm3-pinxKgmacrgmii-pinsxxxx~~~~xxx ~~xx=rmii-pinsxxxxxxxxxxspdifspdif-tx x]hym8563hym8563-intz*pcfg-pull-none-drv-8ma|pcfg-pull-up-drv-8ma}pmicpmic-intzDsdio-pwrseqwifi-enable-hxvbus_hostusb1-en-oczvbus_typecusb0-en-oc zexternal-gmac-clock fixed-clocksY@ clkin_gmac<sdio-pwrseqmmc-pwrseq-simplek &ext_clockdefault >vcc12v-dcin-regulatorregulator-fixed vcc12v_dcin"4Lvcc5v0-sys-regulatorregulator-fixed vcc5v0_sys"4LK@LLK@Fvbus-hostregulator-fixeddefault vbus_hostF Cvbus-typecregulator-fixeddefault vbus_typecF C vccio-flash-regulatorregulator-fixed vccio_flash4w@Lw@ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvqmmc-supplypinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104vmmc-supply#io-channel-cellsdmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-tempinterrupt-namesassigned-clock-parentsclock_in_outphy-modesnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayassigned-clocksphy-supplysnps,reset-gpiophysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-off-in-suspendregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplyflash0-supplygpio1830-supplygpio30-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthreset-gpiosvin-supplyenable-active-high