'8( c@phytec,rk3288-pcm-947phytec,rk3288-phycore-somrockchip,rk3288&7Phytec RK3288 PCM-947aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/i2c@ff140000/rtc@68/i2c@ff650000/pmic@1carm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smp cpu@500-cpuarm,cortex-a129=DXg@u|rcpu@501-cpuarm,cortex-a129=DXg@u|rcpu@502-cpuarm,cortex-a129=DXg@u|rcpu@503-cpuarm,cortex-a129=DXg@u|ropp-table-0operating-points-v2opp-126000000 opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe0000009oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer9  H ua  0pclktimerdisplay-subsystemrockchip,display-subsystem< mmc@ff0c0000rockchip,rk3288-dw-mshcBр uDrv0biuciuciu-driveciu-sampleP 9 @=[resetgokaynxdefault mmc@ff0d0000rockchip,rk3288-dw-mshcBр uEsw0biuciuciu-driveciu-sampleP !9 @=[reset gdisabledmmc@ff0e0000rockchip,rk3288-dw-mshcBр uFtx0biuciuciu-driveciu-sampleP "9@=[reset gdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcBр uGuy0biuciuciu-driveciu-sampleP #9@=[resetgokaynxdefaultsaradc@ff100000rockchip,saradc9 $,uI[0saradcapb_pclk=W [saradc-apbgokay>spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spiuAR0spiclkapb_pclkJ  Otxrx ,default9 gdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spiuBS0spiclkapb_pclkJ Otxrx -default !9 gdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spiuCT0spiclkapb_pclkJOtxrx .default"#$%9gokayflash@0 micron,n25q128a13jedec,spi-nor9Ykgokayi2c@ff140000rockchip,rk3288-i2c9 >0i2cuMdefault&gokaytouchscreen@44 st,stmpe8119Dadc@64maxim,max10379drtc@68rv41629hdefault'&( i2c@ff150000rockchip,rk3288-i2c9 ?0i2cuOdefault)gokayeeprom@51 atmel,24c329Qz i2c@ff160000rockchip,rk3288-i2c9 @0i2cuPdefault*gokayleddimmer@62 nxp,pca95339bled1 red:user1none4led2 green:user2none4led3 blue:user3none4led4 red:user4none4i2c@ff170000rockchip,rk3288-i2c9 A0i2cuQdefault+gokaytserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart9 7uMU0baudclkapb_pclkJOtxrxdefault ,-.gokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart9 8uNV0baudclkapb_pclkJOtxrxdefault/ gdisabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart9i 9uOW0baudclkapb_pclkdefault0gokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart9 :uPX0baudclkapb_pclkJOtxrxdefault1 gdisabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart9 ;uQY0baudclkapb_pclkJ  Otxrxdefault2 gdisableddma-controller@ff250000arm,pl330arm,primecell9%@u 0apb_pclkthermal-zonesreserve-thermal 3cpu-thermald 3tripscpu_alert0'p34passive4cpu_alert1'$34passive5cpu_crit'_3 4criticalcooling-mapsmap0>40Cmap1>50Cgpu-thermald 3tripsgpu_alert0'p34passive6gpu_crit'_3 4criticalcooling-mapsmap0>6 C7tsadc@ff280000rockchip,rk3288-tsadc9( %uHZ0tsadcapb_pclk= [tsadc-apbinitdefaultsleep8R9\8f|:sgokay3ethernet@ff290000rockchip,rk3288-gmac9)macirqeth_wake_irq|:8ufgc]M0stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac=B [stmmacethgokay; inputdefault <=>?!@ ,rgmii-id5 K'B@ `Apymdio0snps,dwmac-mdioethernet-phy@0ethernet-phy-ieee802.3-c229&A?usb@ff500000 generic-ehci9P uBusbgokayusb@ff520000 generic-ohci9R )uBusb gdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc29T u0otghostC usb2-phygokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc29X u0otgotg"1@@ D usb2-phygokayusb@ff5c0000 generic-ehci9\ u gdisableddma-controller@ff600000arm,pl330arm,primecell9`@u 0apb_pclk gdisabledi2c@ff650000rockchip,rk3288-i2c9e <0i2cuLdefaultEgokaypmic@1crockchip,rk8189&FdefaultG@aoH{HHHIHJJregulatorsDCDC_REG1vdd_log 6regulator-state-memNDCDC_REG2vdd_gpu  56regulator-state-memgB@DCDC_REG3vcc_ddr regulator-state-memgDCDC_REG4 vdd_3v3_io 2Z62Zregulator-state-memg2ZDCDC_BOOSTvdd_sys LK@6LK@Hregulator-state-memgLK@SWITCH_REGvdd_sd regulator-state-memNLDO_REG2 vdd_eth_2v5 &%6&%@regulator-state-memg&%LDO_REG3vdd_1v0 B@6B@regulator-state-memgB@LDO_REG4vdd_1v8_lcd_ldo w@6w@regulator-state-memgw@LDO_REG6 vdd_1v0_lcd B@6B@regulator-state-memgB@LDO_REG7 vdd_1v8_ldo w@6w@regulator-state-memNw@LDO_REG9 vdd_io_sd w@62Zregulator-state-memNeeprom@50 atmel,24c329Pz regulator@60 fcs,fan535559` ,vdd_cpu 56@Hi2c@ff660000rockchip,rk3288-i2c9f =0i2cuNdefaultK gdisabledpwm@ff680000rockchip,rk3288-pwm9hdefaultLu_ gdisabledpwm@ff680010rockchip,rk3288-pwm9hdefaultMu_gokaypwm@ff680020rockchip,rk3288-pwm9h defaultNu_ gdisabledpwm@ff680030rockchip,rk3288-pwm9h0defaultOu_ gdisabledsram@ff700000 mmio-sram9ppsmp-sram@0rockchip,rk3066-smp-sram9sram@ff720000#rockchip,rk3288-pmu-srammmio-sram9rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd9spower-controller!rockchip,rk3288-power-controllerh apower-domain@99 uchgfdehilkj$PQRSTUVWXpower-domain@119 uopYZpower-domain@129 u[power-domain@139 u\]reboot-modesyscon-reboot-mode!RB-RB;RB KRBsyscon@ff740000rockchip,rk3288-sgrfsyscon9tclock-controller@ff760000rockchip,rk3288-cru9vu 0xin24m|:WHjk$d#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd9w:edp-phyrockchip,rk3288-dp-phyuh024my gdisabledqio-domains"rockchip,rk3288-io-voltage-domaingokayJusbphyrockchip,rk3288-usb-phygokayusb-phy@320y9 u]0phyclk= [phy-resetDusb-phy@334y94u^0phyclk= [phy-resetBusb-phy@348y9Hu_0phyclk= [phy-resetCwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt9up Ogokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif9 uT 0mclkhclkJ^Otx 6default_|: gdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s9  5uR0i2s_clki2s_hclkJ^^Otxrxdefault`  2 gdisabledcrypto@ff8a0000rockchip,rk3288-crypto9@ 0 u}0aclkhclksclkapb_pclk= [crypto-rstiommu@ff900800rockchip,iommu9@ u 0aclkiface L gdisablediommu@ff914000rockchip,iommu 9@P u 0aclkiface L Y gdisabledrga@ff920000rockchip,rk3288-rga9 uj0aclkhclksclk ta =ilm [coreaxiahbvop@ff930000rockchip,rk3288-vop 9 u0aclk_vopdclk_vophclk_vop ta =def [axiahbdclk bgokayport endpoint@09 cuendpoint@19 drendpoint@29 elendpoint@39 foiommu@ff930300rockchip,iommu9 u 0aclkiface ta  Lgokaybvop@ff940000rockchip,rk3288-vop 9 u0aclk_vopdclk_vophclk_vop ta = [axiahbdclk ggokayport endpoint@09 hvendpoint@19 isendpoint@29 jmendpoint@39 kpiommu@ff940300rockchip,iommu9 u 0aclkiface ta  Lgokaygdsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi9@ u~d 0refpclk ta |: gdisabledportsport@09endpoint@09 leendpoint@19 mjport@19lvds@ff96c000rockchip,rk3288-lvds9@ug 0pclk_lvdslcdcn ta |: gdisabledportsport@09endpoint@09 ofendpoint@19 pkport@19dp@ff970000rockchip,rk3288-dp9@ buic0dppclkqdp ta =o[dp|: gdisabledportsport@09endpoint@09 rdendpoint@19 siport@19hdmi@ff980000rockchip,rk3288-dw-hdmi9 guhmn0iahbisfrcec ta |: gokay tportsport@09endpoint@09 ucendpoint@19 vhport@19video-codec@ff9a0000rockchip,rk3288-vpu9   vepuvdpuu 0aclkhclk w ta iommu@ff9a0800rockchip,iommu9 u 0aclkiface L ta wiommu@ff9c0440rockchip,iommu 9@@@ ou 0aclkiface L gdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t7609$ jobmmugpuuDxX ta  gdisabled7opp-table-1operating-points-v2xopp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon9 \qos@ffaa0080rockchip,rk3288-qossyscon9 ]qos@ffad0000rockchip,rk3288-qossyscon9 Qqos@ffad0100rockchip,rk3288-qossyscon9 Rqos@ffad0180rockchip,rk3288-qossyscon9 Sqos@ffad0400rockchip,rk3288-qossyscon9 Tqos@ffad0480rockchip,rk3288-qossyscon9 Uqos@ffad0500rockchip,rk3288-qossyscon9 Pqos@ffad0800rockchip,rk3288-qossyscon9 Vqos@ffad0880rockchip,rk3288-qossyscon9 Wqos@ffad0900rockchip,rk3288-qossyscon9 Xqos@ffae0000rockchip,rk3288-qossyscon9 [qos@ffaf0000rockchip,rk3288-qossyscon9 Yqos@ffaf0080rockchip,rk3288-qossyscon9 Zdma-controller@ffb20000arm,pl330arm,primecell9@u 0apb_pclk^efuse@ffb40000rockchip,rk3288-efuse9 uq 0pclk_efusecpu-id@79cpu_leakage@179interrupt-controller@ffc01000 arm,gic-400  @9 @ `   pinctrlrockchip,rk3288-pinctrl|: gpio@ff750000rockchip,gpio-bank9u Qu@    Fgpio@ff780000rockchip,gpio-bank9x RuA    gpio@ff790000rockchip,gpio-bank9y SuB    gpio@ff7a0000rockchip,gpio-bank9z TuC    gpio@ff7b0000rockchip,gpio-bank9{ UuD    Agpio@ff7c0000rockchip,gpio-bank9| VuE    (gpio@ff7d0000rockchip,gpio-bank9} WuF    gpio@ff7e0000rockchip,gpio-bank9~ XuG    gpio@ff7f0000rockchip,gpio-bank9 YuH    hdmihdmi-cec-c0 yhdmi-cec-c7 yhdmi-ddc yyhdmi-ddc-unwedge zypcfg-output-low zpcfg-pull-up {pcfg-pull-down |pcfg-pull-none ypcfg-pull-none-12ma  ) }suspendglobal-pwroff yddrio-pwroff yddr0-retention {ddr1-retention {edpedp-hpd  |i2c0i2c0-xfer yyEi2c1i2c1-xfer yy&i2c2i2c2-xfer  y yKi2c3i2c3-xfer yy)i2c4i2c4-xfer yy*i2c5i2c5-xfer yy+i2s0i2s0-bus` yyyyyy`lcdclcdc-ctl@ yyyynsdmmcsdmmc-clk } sdmmc-cmd ~ sdmmc-cd {sdmmc-bus1 {sdmmc-bus4@ ~~~~sdmmc-pwr  ysdio0sdio0-bus1 {sdio0-bus4@ {{{{sdio0-cmd {sdio0-clk ysdio0-cd {sdio0-wp {sdio0-pwr {sdio0-bkpwr {sdio0-int {sdio1sdio1-bus1 {sdio1-bus4@ {{{{sdio1-cd {sdio1-wp {sdio1-bkpwr {sdio1-int {sdio1-cmd {sdio1-clk ysdio1-pwr  {emmcemmc-clk }emmc-cmd }emmc-pwr  {emmc-bus1 {emmc-bus4@ {{{{emmc-bus8 }}}}}}}}spi0spi0-clk  {spi0-cs0  {spi0-tx {spi0-rx {spi0-cs1 {spi1spi1-clk  {spi1-cs0  {!spi1-rx { spi1-tx {spi2spi2-cs1 {spi2-clk {"spi2-cs0 {%spi2-rx {$spi2-tx  {#uart0uart0-xfer {y,uart0-cts {-uart0-rts y.uart1uart1-xfer { y/uart1-cts  {uart1-rts  yuart2uart2-xfer {y0uart3uart3-xfer {y1uart3-cts  {uart3-rts  yuart4uart4-xfer {y2uart4-cts  {uart4-rts  ytsadcotp-pin y8otp-out y9pwm0pwm0-pin yLpwm1pwm1-pin yMpwm2pwm2-pin yNpwm3pwm3-pin yOgmacrgmii-pins yyyy}}}}yyy }}yy<rmii-pins yyyyyyyyyyphy-int {>phy-rst =spdifspdif-tx  y_pcfg-output-high 8ledsuser-led-pin pmicpmic-int {Gpmic-sleep {pcfg-pull-up-drv-12ma  ) ~buttonsuser-button-pins {{rv4162i2c-rtc-int  {'touchscreents-irq-pin yusb_hosthost0-vbus-drv  yhost1-vbus-drv yusb_otgotg-vbus-drv  ymemory-memory9external-gmac-clock fixed-clocksY@ ext_gmac;user-leds gpio-ledsdefaultled-0 green_led D heartbeat Jkeepvdd-emmc-ioregulator-fixed vdd_emmc_iow@6w@vdd-in-otg-outregulator-fixedvdd_in_otg_out LK@6LK@Ivdd-misc-1v8regulator-fixed vdd_misc_1v8 w@6w@Juser-buttons gpio-keysdefaultbutton-0home Xf Dabutton-1menu X Dausb-host0-regulatorregulator-fixed k default vcc_host0_5vLK@6LK@Iusb-host1-regulatorregulator-fixed kdefault vcc_host1_5vLK@6LK@Iusb-otg-regulatorregulator-fixed k default vcc_otg_5vLK@6LK@I #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2rtc0rtc1interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesspi-max-frequencym25p,fast-readpagesizelabellinux,default-triggerreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayti,rx-internal-delayti,tx-internal-delayti,fifo-depthenet-phy-lane-no-swapti,clk-output-selphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyboost-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvddio-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorregulator-enable-ramp-delayregulator-ramp-delayvin-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellssdcard-supplyflash0-supplyflash1-supplygpio1830-supplygpio30-supplybb-supplydvp-supplylcdc-supplywifi-supplyaudio-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highgpiosdefault-statelinux,code