Ð þí›8‘è( ‘°mqmaker,miqirockchip,rk3288& 7mqmaker MiQialiases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000‚/i2c@ff140000‡/i2c@ff660000Œ/i2c@ff150000‘/i2c@ff160000–/i2c@ff170000›/mmc@ff0f0000¡/mmc@ff0c0000§/mmc@ff0d0000­/mmc@ff0e0000³/serial@ff180000»/serial@ff190000Ã/serial@ff690000Ë/serial@ff1b0000Ó/serial@ff1c0000Û/spi@ff110000à/spi@ff120000å/spi@ff130000arm-pmuarm,cortex-a12-pmu0ê—˜™šõcpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@501#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@502#cpuarm,cortex-a12/3:N]œ@krrŒ —cpu@503#cpuarm,cortex-a12/3:N]œ@krrŒ —opp-table-0operating-points-v2Ÿ—opp-126000000ª‚›€± » opp-216000000ª ßæ± » opp-312000000ª˜¾± » opp-408000000ªQ–± » opp-600000000ª#ÃF± » opp-696000000ª)|±~ðopp-816000000ª0£,±B@opp-1008000000ª<ܱopp-1200000000ªG†Œ±Èàopp-1416000000ªTfr±O€opp-1512000000ªZJ±Ö opp-1608000000ª_Ø"±™preserved-memory¿dma-unusable@fe000000/þoscillator fixed-clockÆn6Öxin24mé— timerarm,armv7-timerö0ê   Æn6timer@ff810000rockchip,rk3288-timer/ÿ  êH ka  1pclktimerdisplay-subsystemrockchip,display-subsystem= mmc@ff0c0000rockchip,rk3288-dw-mshcCðÑ€ kÈDrv1biuciuciu-driveciu-sampleQ ê /ÿ @3€\resethokayoy‹œÈ®¹defaultÇ ÑÝmmc@ff0d0000rockchip,rk3288-dw-mshcCðÑ€ kÉEsw1biuciuciu-driveciu-sampleQ ê!/ÿ @3\reset hdisabledmmc@ff0e0000rockchip,rk3288-dw-mshcCðÑ€ kÊFtx1biuciuciu-driveciu-sampleQ ê"/ÿ@3‚\reset hdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcCðÑ€ kËGuy1biuciuciu-driveciu-sampleQ ê#/ÿ@3ƒ\resethokayoyê¹defaultÇÑÝsaradc@ff100000rockchip,saradc/ÿ ê$økI[1saradcapb_pclk3W \saradc-apbhokay spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR1spiclkapb_pclk  txrx ê,¹defaultÇ/ÿ hdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS1spiclkapb_pclk txrx ê-¹defaultÇ !"/ÿ hdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT1spiclkapb_pclktxrx ê.¹defaultÇ#$%&/ÿ hdisabledi2c@ff140000rockchip,rk3288-i2c/ÿ ê>1i2ckM¹defaultÇ'hokayi2c@ff150000rockchip,rk3288-i2c/ÿ ê?1i2ckO¹defaultÇ( hdisabledi2c@ff160000rockchip,rk3288-i2c/ÿ ê@1i2ckP¹defaultÇ)hokayi2c@ff170000rockchip,rk3288-i2c/ÿ êA1i2ckQ¹defaultÇ*hokay—pserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê7%/kMU1baudclkapb_pclktxrx¹defaultÇ+ hdisabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê8%/kNV1baudclkapb_pclktxrx¹defaultÇ, hdisabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿi ê9%/kOW1baudclkapb_pclk¹defaultÇ-hokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê:%/kPX1baudclkapb_pclktxrx¹defaultÇ.hokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ÿ ê;%/kQY1baudclkapb_pclk  txrx¹defaultÇ/ hdisableddma-controller@ff250000arm,pl330arm,primecell/ÿ%@ê<Gbk 1apb_pclk—thermal-zonesreserve-thermalyèˆ0cpu-thermalydˆ0tripscpu_alert0­p¹Ð*passive—1cpu_alert1­$ø¹Ð*passive—2cpu_crit­_¹Ð *criticalcooling-mapsmap0Ä10Éÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1Ä20Éÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermalydˆ0tripsgpu_alert0­p¹Ð*passive—3gpu_crit­_¹Ð *criticalcooling-mapsmap0Ä3 É4ÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3288-tsadc/ÿ( ê%kHZ1tsadcapb_pclk3Ÿ \tsadc-apb¹initdefaultsleepÇ5Ø6â5ì7shokay&=—0ethernet@ff290000rockchip,rk3288-gmac/ÿ)êXmacirqeth_wake_irq78k—fgc˜Ä]M1stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B \stmmacethhokayh—x8input¹defaultÇ9:;<œ=§rgmii° Æ'B@ Û>ë0ôusb@ff500000 generic-ehci/ÿP êkÂý?usb hdisabledusb@ff520000 generic-ohci/ÿR ê)kÂý?usb hdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿT êkÃ1otg hostý@ usb2-phyhokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/ÿX êkÁ1otg  peripheral+=L€€@@ ýA usb2-phyhokayusb@ff5c0000 generic-ehci/ÿ\ êkÄ hdisableddma-controller@ff600000arm,pl330arm,primecell/ÿ`@ê<GbkÁ 1apb_pclk hdisabledi2c@ff650000rockchip,rk3288-i2c/ÿe ê<1i2ckL¹defaultÇBhokayÆ€syr827@40silergy,syr827[/@xvdd_cpu‡ øPŸ™p·ËÝ,ù@C— syr828@41silergy,syr828[/Axvdd_gpu‡ øPŸ™p·C—urtc@51haoyu,hym8563/QéÖxin32kact8846@5aactive-semi,act8846/Z¹defaultÇD1C<CGCRC]CiCuEregulatorsREG1xvcc_ddr·REG2xvcc_io‡2Z Ÿ2Z ·—REG3xvdd_log‡ÈàŸÈà·REG4xvcc_20‡„€Ÿ„€·—EREG5 xvccio_sd‡2Z Ÿ2Z ·—REG6 xvdd10_lcd‡B@ŸB@·REG7xvcca_18‡w@Ÿw@REG8xvcca_33‡2Z Ÿ2Z —YREG9xvcc_lan‡2Z Ÿ2Z —=REG10xvdd_10‡B@ŸB@·REG11xvcc_18‡w@Ÿw@·—REG12 xvcc18_lcd‡w@Ÿw@·i2c@ff660000rockchip,rk3288-i2c/ÿf ê=1i2ckN¹defaultÇFhokaypwm@ff680000rockchip,rk3288-pwm/ÿh¹defaultÇGk_ hdisabledpwm@ff680010rockchip,rk3288-pwm/ÿh¹defaultÇHk_ hdisabledpwm@ff680020rockchip,rk3288-pwm/ÿh ¹defaultÇIk_ hdisabledpwm@ff680030rockchip,rk3288-pwm/ÿh0¹defaultÇJk_ hdisabledsram@ff700000 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1pclk_lvds¹lcdcÇjì] 7 hdisabledportsport@0/endpoint@0/k—bendpoint@1/l—gport@1/dp@ff970000rockchip,rk3288-dp/ÿ—@ êbkic1dppclkýmdpì] 3o\dp7 hdisabledportsport@0/endpoint@0/n—`endpoint@1/o—eport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/ÿ˜/ êgkhmn1iahbisfrcecì] 7~hokaypportsport@0/endpoint@0/q—_endpoint@1/r—dport@1/video-codec@ff9a0000rockchip,rk3288-vpu/ÿšê   XvepuvdpukÐÜ 1aclkhclkúsì] iommu@ff9a0800rockchip,iommu/ÿš ê kÐÜ 1aclkifaceÄì] —siommu@ff9c0440rockchip,iommu /ÿœ@@ÿœ€@ êokÏÛ 1aclkifaceÄ hdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/ÿ£$ê XjobmmugpukÀ:tNì] hokayu—4opp-table-1operating-points-v2—topp-100000000ªõá±~ðopp-200000000ª ë±~ðopp-300000000ªá£±B@opp-400000000ªׄ±Èàopp-600000000ª#ÃF±Ðqos@ffaa0000rockchip,rk3288-qossyscon/ÿª —Wqos@ffaa0080rockchip,rk3288-qossyscon/ÿª€ —Xqos@ffad0000rockchip,rk3288-qossyscon/ÿ­ —Lqos@ffad0100rockchip,rk3288-qossyscon/ÿ­ —Mqos@ffad0180rockchip,rk3288-qossyscon/ÿ­€ —Nqos@ffad0400rockchip,rk3288-qossyscon/ÿ­ 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathgpioslabellinux,default-triggerenable-active-highstartup-delay-us