e8_(?_p$,rockchip,rk3229-evbrockchip,rk3229!7Rockchip RK3229 Evaluation boardaliases=/pinctrl/gpio@11110000C/pinctrl/gpio@11120000I/pinctrl/gpio@11130000O/pinctrl/gpio@11140000U/serial@11010000]/serial@11020000e/serial@11030000m/spi@11090000r/mmc@30020000cpuscpu@f00wcpu,arm,cortex-a7@pscicpu@f01wcpu,arm,cortex-a7pscicpu@f02wcpu,arm,cortex-a7pscicpu@f03wcpu,arm,cortex-a7psciopp-table-0,operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxopp-1296000000M?d7opp-1392000000R<opp-1464000000WB\arm-pmu,arm,cortex-a7-pmu0$LMNO/psci,arm,psci-1.0arm,psci-0.2smctimer,arm,armv7-timerB0$   fn6oscillator ,fixed-clockfn6vxin24m+display-subsystem,rockchip,display-subsystem i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2s @ $i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2s @ $i2s_clki2s_hclkP txrx disabledspdif@100d0000,rockchip,rk3228-spdif  $S mclkhclk txdefault  disabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2s@ $i2s_clki2s_hclkR txrx disabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfd,io-domains",rockchip,rk3228-io-voltage-domainokay  power-controller!,rockchip,rk3228-power-controller2power-domain@48power-domain@5power-domain@6power-domain@7 power-domain@8usb2phy@760,rockchip,rk3228-usb2phy` phyclk vusb480m_phy0okayFotg-port$$;<=otg-bvalidotg-idlinestate+okayEhost-port $> linestate+okay6Gusb2phy@800,rockchip,rk3228-usb2phy phyclk vusb480m_phy1okayHotg-port $D linestate+okay6Ihost-port $E linestate+okay6Jserial@11010000,snps,dw-apb-uart $7fn6MUbaudclkapb_pclkdefault AK disabledserial@11020000,snps,dw-apb-uart $8fn6NVbaudclkapb_pclkdefaultAK disabledserial@11030000,snps,dw-apb-uart $9fn6OWbaudclkapb_pclkdefaultAKokayefuse@11040000,rockchip,rk3228-efuse G pclk_efuseid@7cpu_leakage@17i2c@11050000,rockchip,rk3228-i2c $$i2cLdefault disabledi2c@11060000,rockchip,rk3228-i2c $%i2cMdefault disabledi2c@11070000,rockchip,rk3228-i2c $&i2cNdefault  disabledi2c@11080000,rockchip,rk3228-i2c $'i2cOdefault! disabledspi@11090000,rockchip,rk3228-spi  $1ARspiclkapb_pclkdefault"#$%& disabledwatchdog@110a0000 ,rockchip,rk3228-wdtsnps,dw-wdt  $(b disabledpwm@110b0000,rockchip,rk3288-pwm X^default' disabledpwm@110b0010,rockchip,rk3288-pwm X^default(okayWpwm@110b0020,rockchip,rk3288-pwm X^default)okayXpwm@110b0030,rockchip,rk3288-pwm 0X^default* disabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timer  $+ a+ pclktimerclock-controller@110e0000,rockchip,rk3228-cru+xin24mc,pH}kb$#g0,eррxhррxhdma-controller@110f0000,arm,pl330arm,primecell@$ apb_pclk thermal-zonescpu-thermald-tripscpu_alert0p~passive.cpu_alert1$~passive/cpu_crit_ ~criticalcooling-mapsmap0.0map1/0tsadc@11150000,rockchip,rk3228-tsadc $:HXtsadcapb_pclk}HW #tsadc-apbinitdefaultsleep0/190CYsokayp-hdmi-phy@12030000,rockchip,rk3228-hdmi-phym+sysclkrefoclkrefpclk vhdmiphy_phy+ disabled7gpu@20000000",rockchip,rk3228-maliarm,mali-400 H$gpgpmmupp0ppmmu0pp1ppmmu1 buscore2~ disabledvideo-codec@20020000(,rockchip,rk3228-vpurockchip,rk3399-vpu $   vepuvdpu aclkhclk32iommu@20020800,rockchip,iommu  $  aclkiface23video-codec@20030000*,rockchip,rk3228-vdecrockchip,rk3399-vdec  $ axiahbcabaccore}42iommu@20030480,rockchip,iommu @ @ $ aclkiface24vop@20050000,rockchip,rk3228-vop  $ aclk_vopdclk_vophclk_vopdef #axiahbdclk52 disabledport endpoint@06;iommu@20053f00,rockchip,iommu ? $  aclkiface2 disabled5rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rga  $!aclkhclksclk2kmn #coreaxiahbiommu@20070800,rockchip,iommu  $ aclkiface2 disabledhdmi@200a0000,rockchip,rk3228-dw-hdmi K $#}7l{iahbisfrcecdefault 89:`#hdmi7hdmic, disabledportsport@0endpoint;6port@1mmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@ $  Drvbiuciuciu-driveciu-sampledefault <=> disabledmmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@ $  Eswbiuciuciu-driveciu-sampledefault ?@A disabledmmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@ $f<4`<4` Guybiuciuciu-driveciu-sampledefault BCDS#resetokay 2usb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc20 $otg@otgHZi@ E usb2-phyokayusb@30080000 ,generic-ehci0 $ FGusbokayusb@300a0000 ,generic-ohci0  $ FGusbokayusb@300c0000 ,generic-ehci0  $ HIusbokayusb@300e0000 ,generic-ohci0 $ HIusbokayusb@30100000 ,generic-ehci0 $B HJusbokayusb@30120000 ,generic-ohci0 $C HJusbokayethernet@30200000,rockchip,rk3228-gmac0  $macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8 #stmmacethc,okay}}~ K}xinput6LrgmiidefaultM N 'B@0qos@31030080,rockchip,rk3228-qossyscon1 qos@31030100,rockchip,rk3228-qossyscon1 qos@31030180,rockchip,rk3228-qossyscon1 qos@31030200,rockchip,rk3228-qossyscon1 qos@31040000,rockchip,rk3228-qossyscon1 qos@31050000,rockchip,rk3228-qossyscon1 qos@31060000,rockchip,rk3228-qossyscon1 qos@31070000,rockchip,rk3228-qossyscon1 qos@31070080,rockchip,rk3228-qossyscon1 interrupt-controller@32010000 ,arm,gic-400 22 2@ 2`  $ pinctrl,rockchip,rk3228-pinctrlc,gpio@11110000,rockchip,gpio-bank $3@gpio@11120000,rockchip,gpio-bank $4Agpio@11130000,rockchip,gpio-bank $5BNgpio@11140000,rockchip,gpio-bank $6CSpcfg-pull-up$Rpcfg-pull-down1Qpcfg-pull-none@Ppcfg-pull-none-drv-12maM Osdmmcsdmmc-clk\O<sdmmc-cmd\O=sdmmc-bus4@\OOOO>sdiosdio-clk\O?sdio-cmd\O@sdio-bus4@\OOOOAemmcemmc-clk\PBemmc-cmd\PCemmc-bus8\PPPPPPPPDgmacrgmii-pins\P PPOOOO O OPPPP PPMrmii-pins\P PPOO OPPPPphy-pins \PPhdmihdmi-hpd\Q9hdmii2c-xfer \PP8hdmi-cec\P:i2c0i2c0-xfer \PPi2c1i2c1-xfer \PPi2c2i2c2-xfer \PP i2c3i2c3-xfer \PP!spi0spi0-clk\ R"spi0-cs0\R%spi0-tx\ R#spi0-rx\ R$spi0-cs1\ R&spi1spi1-clk\Rspi1-cs0\Rspi1-rx\Rspi1-tx\Rspi1-cs1\Ri2s1i2s1-bus\P P P P PPPPP pwm0pwm0-pin\P'pwm1pwm1-pin\P(pwm2pwm2-pin\ P)pwm3pwm3-pin\ P*spdifspdif-tx\P tsadcotp-pin\P0otp-out\P1uart0uart0-xfer \PPuart0-cts\Puart0-rts\Puart1uart1-xfer \ P Puart1-cts\Puart1-rts\ Puart2uart2-xfer \RPuart21-xfer \ R Puart2-cts\Puart2-rts\Pkeyspwr-key\RYusbhost-vbus-drv\PTmemory@60000000wmemory`@dc-12v-regulator,regulator-fixedjdc_12vyVext_gmac ,fixed-clockfsY@ vext_gmacKvcc-host-regulator,regulator-fixed SdefaultT jvcc_hostyUvcc-phy-regulator,regulator-fixedjvcc_phyw@w@yLvcc-sys-regulator,regulator-fixedjvcc_sysyLK@LK@VUvccio-1v8-regulator,regulator-fixed jvccio_1v8w@w@yUvccio-3v3-regulator,regulator-fixed jvccio_3v32Z2ZyU vdd-arm-regulator,pwm-regulatorWaUjvdd_arm~\yvdd-log-regulator,pwm-regulatorXaUjvdd_logB@ ygpio-keys ,gpio-keysdefaultYpower-keyGPIO Key Power Std1 #address-cells#size-cellsinterrupt-parentcompatiblemodelgpio0gpio1gpio2gpio3serial0serial1serial2spi0mmc0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsclock-namesdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supply#power-domain-cellspm_qosinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#dma-cellsarm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-modepower-domainsiommus#iommu-cellsremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeednon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplypwmspwm-supplyautorepeatlabelgpioslinux,codedebounce-intervalwakeup-source