]8XD(X !,Rockchip RK3228 Evaluation board$2rockchip,rk3228-evbrockchip,rk3228aliases=/pinctrl/gpio@11110000C/pinctrl/gpio@11120000I/pinctrl/gpio@11130000O/pinctrl/gpio@11140000U/serial@11010000]/serial@11020000e/serial@11030000m/spi@11090000r/mmc@30020000cpuscpu@f00wcpu2arm,cortex-a7@pscicpu@f01wcpu2arm,cortex-a7pscicpu@f02wcpu2arm,cortex-a7pscicpu@f03wcpu2arm,cortex-a7psciopp-table-02operating-points-v2opp-408000000Q~@ opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxarm-pmu2arm,cortex-a7-pmu0LMNO$psci2arm,psci-1.0arm,psci-0.2smctimer2arm,armv7-timer70   [n6oscillator 2fixed-clock[n6kxin24m~'display-subsystem2rockchip,display-subsystemi2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2s @ i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2s @ i2s_clki2s_hclkP txrx disabledspdif@100d00002rockchip,rk3228-spdif  S mclkhclk txdefault  disabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2s@ i2s_clki2s_hclkR txrx disabledsyscon@11000000&2rockchip,rk3228-grfsysconsimple-mfd(io-domains"2rockchip,rk3228-io-voltage-domain disabledpower-controller!2rockchip,rk3228-power-controller.power-domain@48 power-domain@5power-domain@6power-domain@7 power-domain@8usb2phy@7602rockchip,rk3228-usb2phy` phyclk kusb480m_phy0~ disabledBotg-port$;<=otg-bvalidotg-idlinestate disabledAhost-port > linestate disabledCusb2phy@8002rockchip,rk3228-usb2phy phyclk kusb480m_phy1~ disabledDotg-port D linestate disabledEhost-port E linestate disabledFserial@110100002snps,dw-apb-uart 7[n6MUbaudclkapb_pclkdefault   disabledserial@110200002snps,dw-apb-uart 8[n6NVbaudclkapb_pclkdefault  disabledserial@110300002snps,dw-apb-uart 9[n6OWbaudclkapb_pclkdefault okayefuse@110400002rockchip,rk3228-efuse G pclk_efuseid@7cpu_leakage@17i2c@110500002rockchip,rk3228-i2c $i2cLdefault disabledi2c@110600002rockchip,rk3228-i2c %i2cMdefault disabledi2c@110700002rockchip,rk3228-i2c &i2cNdefault disabledi2c@110800002rockchip,rk3228-i2c 'i2cOdefault disabledspi@110900002rockchip,rk3228-spi  1ARspiclkapb_pclkdefault !" disabledwatchdog@110a0000 2rockchip,rk3228-wdtsnps,dw-wdt  (b disabledpwm@110b00002rockchip,rk3288-pwm ^default# disabledpwm@110b00102rockchip,rk3288-pwm ^default$ disabledpwm@110b00202rockchip,rk3288-pwm ^default% disabledpwm@110b00302rockchip,rk3288-pwm 0^default& disabledtimer@110c0000,2rockchip,rk3228-timerrockchip,rk3288-timer  + a' pclktimerclock-controller@110e00002rockchip,rk3228-cru'xin24m#(~0H=kb$M#g0,eррxhррxhdma-controller@110f00002arm,pl330arm,primecell@bm apb_pclk thermal-zonescpu-thermald)tripscpu_alert0p~passive*cpu_alert1$~passive+cpu_crit_ ~criticalcooling-mapsmap0*0map1+0tsadc@111500002rockchip,rk3228-tsadc :HXtsadcapb_pclk=HMW tsadc-apbinitdefaultsleep,-,sokay0G)hdmi-phy@120300002rockchip,rk3228-hdmi-phym'sysclkrefoclkrefpclk~ khdmiphy_phy disabled3gpu@20000000"2rockchip,rk3228-maliarm,mali-400 Hgpgpmmupp0ppmmu0pp1ppmmu1 buscoreb.~ disabledvideo-codec@20020000(2rockchip,rk3228-vpurockchip,rk3399-vpu    vepuvdpu aclkhclkp/b.iommu@200208002rockchip,iommu    aclkifaceb.w/video-codec@20030000*2rockchip,rk3228-vdecrockchip,rk3399-vdec   axiahbcabaccore=Mp0b.iommu@200304802rockchip,iommu @ @  aclkifaceb.w0vop@200500002rockchip,rk3228-vop   aclk_vopdclk_vophclk_vopdef axiahbdclkp1b. disabledportendpoint@027iommu@20053f002rockchip,iommu ?   aclkifaceb.w disabled1rga@20060000(2rockchip,rk3228-rgarockchip,rk3288-rga  !aclkhclksclkb.kmn coreaxiahbiommu@200708002rockchip,iommu   aclkifaceb.w disabledhdmi@200a00002rockchip,rk3228-dw-hdmi   #=3l{iahbisfrcecdefault 456`hdmi3hdmi#( disabledportsport@0endpoint72port@1mmc@3000000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@   Drvbiuciuciu-driveciu-sampledefault 89: disabledmmc@3001000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@   Eswbiuciuciu-driveciu-sampledefault ;<= disabledmmc@3002000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@ [<4`<4` Guybiuciuciu-driveciu-sampledefault >?@Sresetokay %usb@3004000022rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc20 otg3otg;M\@ A usb2-phy disabledusb@30080000 2generic-ehci0  BCusb disabledusb@300a0000 2generic-ohci0   BCusb disabledusb@300c0000 2generic-ehci0   DEusb disabledusb@300e0000 2generic-ohci0  DEusb disabledusb@30100000 2generic-ehci0 B DFusb disabledusb@30120000 2generic-ohci0 C DFusb disabledethernet@302000002rockchip,rk3228-gmac0  macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8 stmmaceth#(okay=|MkoutputxGrmiiHmdio2snps,dwmac-mdioethernet-phy@042ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22?Hqos@310300802rockchip,rk3228-qossyscon1  qos@310301002rockchip,rk3228-qossyscon1 qos@310301802rockchip,rk3228-qossyscon1  qos@310302002rockchip,rk3228-qossyscon1 qos@310400002rockchip,rk3228-qossyscon1 qos@310500002rockchip,rk3228-qossyscon1 qos@310600002rockchip,rk3228-qossyscon1 qos@310700002rockchip,rk3228-qossyscon1 qos@310700802rockchip,rk3228-qossyscon1 interrupt-controller@32010000 2arm,gic-400 22 2@ 2`   pinctrl2rockchip,rk3228-pinctrl#(gpio@111100002rockchip,gpio-bank 3@gpio@111200002rockchip,gpio-bank 4Agpio@111300002rockchip,gpio-bank 5Bgpio@111400002rockchip,gpio-bank 6Cpcfg-pull-upLpcfg-pull-downKpcfg-pull-noneJpcfg-pull-none-drv-12ma Isdmmcsdmmc-clk*I8sdmmc-cmd*I9sdmmc-bus4@*IIII:sdiosdio-clk*I;sdio-cmd*I<sdio-bus4@*IIII=emmcemmc-clk*J>emmc-cmd*J?emmc-bus8*JJJJJJJJ@gmacrgmii-pins*J JJIIII I IJJJJ JJrmii-pins*J JJII IJJJJphy-pins *JJhdmihdmi-hpd*K5hdmii2c-xfer *JJ4hdmi-cec*J6i2c0i2c0-xfer *JJi2c1i2c1-xfer *JJi2c2i2c2-xfer *JJi2c3i2c3-xfer *JJspi0spi0-clk* Lspi0-cs0*L!spi0-tx* Lspi0-rx* L spi0-cs1* L"spi1spi1-clk*Lspi1-cs0*Lspi1-rx*Lspi1-tx*Lspi1-cs1*Li2s1i2s1-bus*J J J J JJJJJ pwm0pwm0-pin*J#pwm1pwm1-pin*J$pwm2pwm2-pin* J%pwm3pwm3-pin* J&spdifspdif-tx*J tsadcotp-pin*J,otp-out*J-uart0uart0-xfer *JJuart0-cts*Juart0-rts*Juart1uart1-xfer * J Juart1-cts*Juart1-rts* Juart2uart2-xfer *LJuart21-xfer * L Juart2-cts*Juart2-rts*Jmemory@60000000wmemory`@vcc-phy-regulator2regulator-fixed8Kvcc_phyZw@rw@G #address-cells#size-cellsinterrupt-parentmodelcompatiblegpio0gpio1gpio2gpio3serial0serial1serial2spi0mmc0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsclock-namesdmasdma-namespinctrl-namespinctrl-0status#power-domain-cellspm_qosinterrupt-names#phy-cellsreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#dma-cellsarm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypower-domainsiommus#iommu-cellsremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-supplyphy-modephy-handlephy-is-integratedinterrupt-controller#interrupt-cellsrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on