(8( Xgoogle,veyron-fievel-rev8google,veyron-fievel-rev7google,veyron-fievel-rev6google,veyron-fievel-rev5google,veyron-fievel-rev4google,veyron-fievel-rev3google,veyron-fievel-rev2google,veyron-fievel-rev1google,veyron-fievel-rev0google,veyron-fievelgoogle,veyronrockchip,rk3288&7Google Fievelaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/mmc@ff0f0000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 ,@:Ar[ gcpu@501cpuarm,cortex-a12 ,@:Argcpu@502cpuarm,cortex-a12 ,@:Argcpu@503cpuarm,cortex-a12 ,@:Argopp-table-0operating-points-v2ogopp-126000000z opp-216000000z  opp-408000000zQ opp-600000000z#F opp-696000000z)|~opp-816000000z0,B@opp-1008000000z<opp-1200000000zGopp-1416000000zTfrOopp-1512000000zZJopp-1608000000z_" opp-1704000000zepopp-1800000000zkI\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mg timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H :a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр :Drvbiuciuciu-driveciu-sample!  @,reset 8disabledmmc@ff0d0000rockchip,rk3288-dw-mshcр :Eswbiuciuciu-driveciu-sample! ! @,reset8okay?IZg} default btmrvl@2marvell,sd8897-bt& defaultmmc@ff0e0000rockchip,rk3288-dw-mshcр :Ftxbiuciuciu-driveciu-sample! "@,reset 8disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр :Guybiuciuciu-driveciu-sample! #@,reset8okay?!?J}default saradc@ff100000rockchip,saradc $Y:I[saradcapb_pclkW ,saradc-apb 8disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi:ARspiclkapb_pclkk  ptxrx ,default 8disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi:BSspiclkapb_pclkk ptxrx -default ! 8disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi:CTspiclkapb_pclkkptxrx .default"#$%8okayz flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c:Mdefault&8okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c:Odefault' 8disabledi2c@ff160000rockchip,rk3288-i2c @i2c:Pdefault(8okay2,ts3a227e@3b ti,ts3a227e;&)default*gi2c@ff170000rockchip,rk3288-i2c Ai2c:Qdefault+ 8disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7:MUbaudclkapb_pclkkptxrxdefault ,-.8okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8:NVbaudclkapb_pclkkptxrxdefault/8okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9:OWbaudclkapb_pclkdefault08okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart ::PXbaudclkapb_pclkkptxrxdefault1 8disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;:QYbaudclkapb_pclkk  ptxrxdefault2 8disableddma-controller@ff250000arm,pl330arm,primecell%@.: apb_pclkgthermal-zonesreserve-thermalE[i3cpu-thermalEd[i3tripscpu_alert0yppassiveg4cpu_alert1y$passiveg5cpu_crity criticalcooling-mapsmap040map150gpu-thermalEd[i3tripsgpu_alert0y4passiveg6gpu_crity criticalcooling-mapsmap06 7tsadc@ff280000rockchip,rk3288-tsadc( %:HZtsadcapb_pclk ,tsadc-apbinitdefaultsleep898:H8okay g3ethernet@ff290000rockchip,rk3288-gmac)$macirqeth_wake_irq:8:fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB ,stmmaceth8okay4D;[inputh<srgmii|=default>?@A0  'u0mdio0snps,dwmac-mdioethernet-phy@1g<usb@ff500000 generic-ehciP :Busb8okayusb@ff520000 generic-ohciR ):Busb 8disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T :otghostC usb2-phy8okay&usb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X :otghost=O^@@ D usb2-phy8okay4zDD&usb@ff5c0000 generic-ehci\ : 8disableddma-controller@ff600000arm,pl330arm,primecell`@.: apb_pclk 8disabledi2c@ff650000rockchip,rk3288-i2ce <i2c:LdefaultE8okay2dpmic@1brockchip,rk808xin32kwifibt_32kin&)default FGHmI J JKgregulatorsDCDC_REG1 vdd_arm/CU qm qg regulator-state-memDCDC_REG2 vdd_gpu/CU 5mqgregulator-state-memDCDC_REG3  vcc135_ddr/Cregulator-state-memDCDC_REG4 vcc_18/CUw@mw@gregulator-state-memw@LDO_REG3 vdd_10/CUB@mB@regulator-state-memB@LDO_REG7  vdd10_lcd/CUB@mB@regulator-state-memSWITCH_REG1  vcc33_lcd/Cgaregulator-state-memLDO_REG6  vcc18_codec/CUw@mw@gbregulator-state-memLDO_REG2/CUw@mw@  vdd18_lcdtregulator-state-memLDO_REG8/CU2Zm2Z  vcc33_ccdregulator-state-memSWITCH_REG2  vcc33_lang=i2c@ff660000rockchip,rk3288-i2cf =i2c:NdefaultL8okay2 max98090@10maxim,max98090&Mmclk:qdefaultNgpwm@ff680000rockchip,rk3288-pwmhdefaultO:_ 8disabledpwm@ff680010rockchip,rk3288-pwmhdefaultP:_8okaygpwm@ff680020rockchip,rk3288-pwmh defaultQ:_ 8disabledpwm@ff680030rockchip,rk3288-pwmh0defaultR:_ 8disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsgpower-controller!rockchip,rk3288-power-controller4hD gfpower-domain@9 :chgfdehilkj$STUVWXYZ[power-domain@11 :op\]power-domain@12 :^power-domain@13 :_`reboot-modesyscon-reboot-mode RB RB.RB >RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv: xin24m:JH4jk$W#gׄeрxhрxhgsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwg:edp-phyrockchip,rk3288-dp-phy:h24ml 8disabledgvio-domains"rockchip,rk3288-io-voltage-domain8okaywIIIabusbphyrockchip,rk3288-usb-phy8okayusb-phy@320l :]phyclk ,phy-resetgDusb-phy@334l4:^phyclk ,phy-resetgBusb-phy@348lH:_phyclk ,phy-resetgCwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt:p O8okaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif:T mclkhclkkcptx 6defaultd: 8disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5:Ri2s_clki2s_hclkkccptxrxdefaulte 8okaygcrypto@ff8a0000rockchip,rk3288-crypto@ 0 :}aclkhclksclkapb_pclk ,crypto-rstiommu@ff900800rockchip,iommu@ : aclkiface # 8disablediommu@ff914000rockchip,iommu @P : aclkiface # 0 8disabledrga@ff920000rockchip,rk3288-rga :jaclkhclksclk Kf ilm ,coreaxiahbvop@ff930000rockchip,rk3288-vop  :aclk_vopdclk_vophclk_vop Kf def ,axiahbdclk Yg8okayportg endpoint@0 `hg{endpoint@1 `igwendpoint@2 `jgqendpoint@3 `kgtiommu@ff930300rockchip,iommu : aclkiface Kf  #8okayggvop@ff940000rockchip,rk3288-vop  :aclk_vopdclk_vophclk_vop Kf  ,axiahbdclk Yl 8disabledportg endpoint@0 `mg|endpoint@1 `ngxendpoint@2 `ogrendpoint@3 `pguiommu@ff940300rockchip,iommu : aclkiface Kf  # 8disabledgldsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ :~d refpclk Kf : 8disabledportsport@0endpoint@0 `qgjendpoint@1 `rgoport@1lvds@ff96c000rockchip,rk3288-lvds@:g pclk_lvdslcdcs Kf : 8disabledportsport@0endpoint@0 `tgkendpoint@1 `ugpport@1dp@ff970000rockchip,rk3288-dp@ b:icdppclkvdp Kf o,dp: 8disabledportsport@0endpoint@0 `wgiendpoint@1 `xgnport@1hdmi@ff980000rockchip,rk3288-dw-hdmi: g:hmniahbisfrcec Kf 8okaydefaultunwedgeyzgportsportendpoint@0 `{ghendpoint@1 `|gmvideo-codec@ff9a0000rockchip,rk3288-vpu   $vepuvdpu: aclkhclk Y} Kf iommu@ff9a0800rockchip,iommu : aclkiface # Kf g}iommu@ff9c0440rockchip,iommu @@@ o: aclkiface # 8disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ $jobmmugpu: ~ Kf 8okay pg7opp-table-1operating-points-v2g~opp-100000000z~opp-200000000z ~opp-300000000zB@opp-400000000zׄopp-600000000z#Fqos@ffaa0000rockchip,rk3288-qossyscon g_qos@ffaa0080rockchip,rk3288-qossyscon g`qos@ffad0000rockchip,rk3288-qossyscon gTqos@ffad0100rockchip,rk3288-qossyscon gUqos@ffad0180rockchip,rk3288-qossyscon gVqos@ffad0400rockchip,rk3288-qossyscon gWqos@ffad0480rockchip,rk3288-qossyscon gXqos@ffad0500rockchip,rk3288-qossyscon gSqos@ffad0800rockchip,rk3288-qossyscon gYqos@ffad0880rockchip,rk3288-qossyscon gZqos@ffad0900rockchip,rk3288-qossyscon g[qos@ffae0000rockchip,rk3288-qossyscon g^qos@ffaf0000rockchip,rk3288-qossyscon g\qos@ffaf0080rockchip,rk3288-qossyscon g]dma-controller@ffb20000arm,pl330arm,primecell@.: apb_pclkgcefuse@ffb40000rockchip,rk3288-efuse :q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400 | @ @ `   gpinctrlrockchip,rk3288-pinctrl:defaultsleepgpio@ff750000rockchip,gpio-banku Q:@   |  PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LHUB_USB1_nFALUTPHY_PMEBPHY_INTRECOVERY_SW_LOTP_OUTUSB_OTG_POWER_ENAP_WARM_RESET_HUSB_OTG_nFALUTI2C0_SDA_PMICI2C0_SCL_PMICDEVMODE_LUSB_INTg)gpio@ff780000rockchip,gpio-bankx R:A   | gpio@ff790000rockchip,gpio-banky S:B   | i CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TPggpio@ff7a0000rockchip,gpio-bankz T:C   |  FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7VCC5V_GOOD_HFLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOPHY_TXD2PHY_TXD3MAC_RXD2MAC_RXD3PHY_TXD0PHY_TXD1MAC_RXD0MAC_RXD1gpio@ff7b0000rockchip,gpio-bank{ U:D   |  MAC_MDCMAC_RXDVMAC_RXERMAC_CLKPHY_TXENMAC_MDIOMAC_RXCLKPHY_RSTPHY_TXCLKUART0_RXDUART0_TXDUART0_CTS_LUART0_RTS_LSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEggpio@ff7c0000rockchip,gpio-bank| V:E   |  USB_OTG_CTL1HUB_USB2_CTL1HUB_USB2_PWR_ENHUB_USB_ILIM_SELUSB_OTG_STATUS_LHUB_USB1_CTL1HUB_USB1_PWR_ENVCC50_HDMI_ENggpio@ff7d0000rockchip,gpio-bank} W:F   |  I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETHUB_USB2_nFALUTUSB_OTG_ILIM_SELgMgpio@ff7e0000rockchip,gpio-bank~ X:G   |  LCD_BL_PWMPWM_LOGBL_ENPWR_LED1TPM_INT_HSPK_ONAP_FLASH_WP_LCPU_NMIDVSOKEDP_HPDDVS1LCD_ENDVS2HDMI_CECI2C4_SDAI2C4_SCLI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDgJgpio@ff7f0000rockchip,gpio-bank Y:H   | ^ RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc gyhdmi-ddc-unwedge gzvcc50-hdmi-en gpcfg-output-low gpcfg-pull-up gpcfg-pull-down gpcfg-pull-none gpcfg-pull-none-12ma   gsuspendglobal-pwroff gddrio-pwroff gddr0-retention gddr1-retention edpedp-hpd  i2c0i2c0-xfer gEi2c1i2c1-xfer g&i2c2i2c2-xfer   gLi2c3i2c3-xfer g'i2c4i2c4-xfer g(i2c5i2c5-xfer g+i2s0i2s0-bus` gelcdclcdc-ctl@ gssdmmcsdmmc-clk sdmmc-cmd sdmmc-cd sdmmc-bus1 sdmmc-bus4@ sdio0sdio0-bus1 sdio0-bus4@ gsdio0-cmd gsdio0-clk gsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h gbt-enable-l bt-host-wake bt-host-wake-l gbt-dev-wake-sleep gbt-dev-wake-awake gbt-dev-wake sdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk gemmc-cmd gemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 gemmc-reset  gspi0spi0-clk  gspi0-cs0  gspi0-tx gspi0-rx gspi0-cs1 spi1spi1-clk  gspi1-cs0  g!spi1-rx g spi1-tx gspi2spi2-cs1 spi2-clk g"spi2-cs0 g%spi2-rx g$spi2-tx  g#uart0uart0-xfer g,uart0-cts g-uart0-rts g.uart1uart1-xfer  g/uart1-cts  uart1-rts  uart2uart2-xfer g0uart3uart3-xfer g1uart3-cts  uart3-rts  uart4uart4-xfer g2uart4-cts  uart4-rts  tsadcotp-pin g8otp-out g9pwm0pwm0-pin gOpwm1pwm1-pin gPpwm2pwm2-pin gQpwm3pwm3-pin gRgmacrgmii-pins  g>rmii-pins phy-rst g?phy-pmeb g@phy-int gAspdifspdif-tx  gdpcfg-pull-none-drv-8ma  gpcfg-pull-up-drv-8ma  pcfg-output-high gbuttonspwr-key-l gpmicpmic-int-l gFdvs-1  gGdvs-2 gHrebootap-warm-reset-h grecovery-switchrec-mode-l tpmtpm-int-h write-protectfw-wp-ap codechp-det gint-codec gNmic-det  gheadsetts3a227e-int-l g*buck-5vdrv-5v gledspwr-led1-on gpwr-led1-blink gusb-bc12usb-otg-ilim-sel gusb-usb-ilim-sel gusb-hosthub_usb1_pwr_en ghub_usb2_pwr_en gusb_otg_pwr_en gchosen +serial2:115200n8memorymemorypower-button gpio-keysdefaultkey-power 7Power  ) =t Hdgpio-restart gpio-restart  ) default Zemmc-pwrseqmmc-pwrseq-emmcdefault c gsdio-pwrseqmmc-pwrseq-simple: ext_clockdefault cg vcc-5vregulator-fixed vcc_5v/CULK@mLK@ o JdefaultgKvcc33-sysregulator-fixed  vcc33_sys/CU2Zm2Zgvcc50-hdmiregulator-fixed  vcc50_hdmi/C K o defaultvdd-logicpwm-regulator  vdd_logic   { /CU~mpsound!rockchip,rockchip-audio-max98090default VEYRON-I2S   M M  - Dvccsysregulator-fixed vccsysC/vcc33-ioregulator-fixed/C  vcc33_iogIvcc5-host1-regulatorregulator-fixed o default  vcc5_host1/Cvcc5-host2-regulatorregulator-fixed o default  vcc5_host2/Cvcc5v-otg-regulatorregulator-fixed o ) default  vcc5_otg/Cexternal-gmac-clock fixed-clocksY@ ext_gmacg; #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymarvell,wakeup-pincap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-modephy-supplyrx_delaytx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-uswakeup-sourcephysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosenable-active-highvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codec