:8T( radxa,rock-5arockchip,rk3588s +7Radxa ROCK 5 Model Aaliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/ethernet@fe1c0000/mmc@fe2e0000/mmc@fe2c0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0 cpuarm,cortex-a55psci': A Q0,f v@@  cpu@100 cpuarm,cortex-a55psci': f v@@ cpu@200 cpuarm,cortex-a55psci': f v@@ cpu@300 cpuarm,cortex-a55psci': f v@@ cpu@400 cpuarm,cortex-a76psci': A Q0,f v@@cpu@500 cpuarm,cortex-a76psci': f v@@cpu@600 cpuarm,cortex-a76psci': A Q0,f v@@cpu@700 cpuarm,cortex-a76psci': f v@@ idle-statespscicpu-sleeparm,idle-state(9Pdaxq l2-cache-l0cachex@ l2-cache-l1cachex@l2-cache-l2cachex@l2-cache-l3cachex@l2-cache-b0cachex@l2-cache-b1cachex@l2-cache-b2cachex@l2-cache-b3cachex@l3-cachecachex0@firmwareopteelinaro,optee-tz smcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0 smcclock-0 fixed-clock)׫splldisplay-subsystemrockchip,display-subsystemtimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram +sram@0arm,scmi-shmemusb@fc800000"rockchip,rk3588-ehcigeneric-ehci:usb!/okay6defaultD !"#$usb@fc840000"rockchip,rk3588-ohcigeneric-ohci:usb!/okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci:%&usb!/okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci:%&usb!/okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(:jihkr&Nref_clksuspend_clkbus_clkutmipipeZhost' usb3-phy butmi_widek4r/okaysyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXksyscon@fd58c000rockchip,rk3588-sys-grfsysconX-syscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ .syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ/syscon@fd5b0000rockchip,rk3588-php-grfsyscon[)syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@8000rockchip,rk3588-usb2phykophyapb:Nphyclk usb480m_phy2/okayhost-port/okay(syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@c000rockchip,rk3588-usb2phykp phyapb:Nphyclk usb480m_phy3/okay%host-port/okay(&syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram` `+clock-controller@fd7c0000rockchip,rk3588-cru|A]q@QA.2Fq)׫ׄe/ׄ eZ р *)i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=:ts Ni2cpclkD*6default+/okayregulator@42rockchip,rk8602B7Tvdd_cpu_big0_s0cwdp+regulator-state-memregulator@43 rockchip,rk8603rockchip,rk8602C7Tvdd_cpu_big1_s0cwdp+regulator-state-memvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8:]\abcd[7Naclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop,!*-./%0 /disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~:]\ Naclkiface2! /disabled,serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK:Nbaudclkapb_pclk?11DtxrxD26defaultNX /disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm: NpwmpclkD36defaulte /disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm: NpwmpclkD46defaulte /disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm : NpwmpclkD56defaulte /disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0: NpwmpclkD66defaulte/okaypower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd0power-controller!rockchip,rk3588-power-controllerp+/okaypower-domain@8p+power-domain@9  :!#" 789p+power-domain@10 :!#":ppower-domain@11 :!#";ppower-domain@12 :<=>?ppower-domain@13 +ppower-domain@14(:@ppower-domain@15 :Appower-domain@16: BCD+ppower-domain@17 : EFGppower-domain@21: HIJKLMNO+ppower-domain@23:CAPppower-domain@14 :@ppower-domain@15:Appower-domain@22:Qppower-domain@24:[Z]RS+ppower-domain@258:ZTppower-domain@268:QUVppower-domain@270:WXYZ+ppower-domain@28 :[\ppower-domain@29(:]^ppower-domain@30:z{_ppower-domain@31@:W`abcppower-domain@33!:WZ[ppower-domain@34":WZ[ppower-domain@37%:2dppower-domain@38&:45ppower-domain@40(epi2s@fddc0000rockchip,rk3588-i2s-tdm:Nmclk_txmclk_rxhclkA?fDtx!ktx-m /disabledi2s@fddf0000rockchip,rk3588-i2s-tdm:445Nmclk_txmclk_rxhclkA1?fDtx!ktx-m /disabledi2s@fddfc000rockchip,rk3588-i2s-tdm:00,Nmclk_txmclk_rxhclkA-?fDrx!krx-m /disabledqos@fdf35000rockchip,rk3588-qossysconP <qos@fdf35200rockchip,rk3588-qossysconR =qos@fdf35400rockchip,rk3588-qossysconT >qos@fdf35600rockchip,rk3588-qossysconV ?qos@fdf36000rockchip,rk3588-qossyscon` _qos@fdf39000rockchip,rk3588-qossyscon dqos@fdf3d800rockchip,rk3588-qossyscon eqos@fdf3e000rockchip,rk3588-qossyscon aqos@fdf3e200rockchip,rk3588-qossyscon `qos@fdf3e400rockchip,rk3588-qossyscon bqos@fdf3e600rockchip,rk3588-qossyscon cqos@fdf40000rockchip,rk3588-qossyscon ]qos@fdf40200rockchip,rk3588-qossyscon ^qos@fdf40400rockchip,rk3588-qossyscon Wqos@fdf40500rockchip,rk3588-qossyscon Xqos@fdf40600rockchip,rk3588-qossyscon Yqos@fdf40800rockchip,rk3588-qossyscon Zqos@fdf41000rockchip,rk3588-qossyscon [qos@fdf41100rockchip,rk3588-qossyscon \qos@fdf60000rockchip,rk3588-qossyscon Bqos@fdf60200rockchip,rk3588-qossyscon Cqos@fdf60400rockchip,rk3588-qossyscon Dqos@fdf61000rockchip,rk3588-qossyscon Eqos@fdf61200rockchip,rk3588-qossyscon Fqos@fdf61400rockchip,rk3588-qossyscon Gqos@fdf62000rockchip,rk3588-qossyscon @qos@fdf63000rockchip,rk3588-qossyscon0 Aqos@fdf64000rockchip,rk3588-qossyscon@ Pqos@fdf66000rockchip,rk3588-qossyscon` Hqos@fdf66200rockchip,rk3588-qossysconb Iqos@fdf66400rockchip,rk3588-qossyscond Jqos@fdf66600rockchip,rk3588-qossysconf Kqos@fdf66800rockchip,rk3588-qossysconh Lqos@fdf66a00rockchip,rk3588-qossysconj Mqos@fdf66c00rockchip,rk3588-qossysconl Nqos@fdf66e00rockchip,rk3588-qossysconn Oqos@fdf67000rockchip,rk3588-qossysconp Qqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon :qos@fdf71000rockchip,rk3588-qossyscon ;qos@fdf72000rockchip,rk3588-qossyscon 7qos@fdf72200rockchip,rk3588-qossyscon" 8qos@fdf72400rockchip,rk3588-qossyscon$ 9qos@fdf80000rockchip,rk3588-qossyscon Tqos@fdf81000rockchip,rk3588-qossyscon Uqos@fdf81200rockchip,rk3588-qossyscon Vqos@fdf82000rockchip,rk3588-qossyscon Rqos@fdf82200rockchip,rk3588-qossyscon" Spcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0:CH>MR)Naclk_mstaclk_slvaclk_dbipclkauxpipe pciPsyspmcmsglegacyerr`gggg0h0' pcie-phy!"T  @ @0 @@dbiapbconfigk). pwrpipe+ /disabledlegacy-interrupt-controller! gpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0:DI?NSs)Naclk_mstaclk_slvaclk_dbipclkauxpipe pciPsyspmcmsglegacyerr`iiii@h@j pcie-phy!"T  @ @0 A@dbiapbconfigk*/ pwrpipe+ /disabledlegacy-interrupt-controller! idfi@fe060000rockchip,rk3588-dfi@&0:%kethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(:67Y^50Nstmmacethclk_mac_refpclk_macaclk_macptp_ref!!k$ stmmaceth*-6)GlWhm{n/okayoutputorgmiiDpqrst6default:>mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c9166defaultDuN  vostmmac-axi-configlrx-queues-config"mqueue0queue1tx-queues-config8nqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(:b_eToNsatapmaliverxoobrefasicN+ /disabledsata-port@0`@j sata-phym | sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(:dagVqNsatapmaliverxoobrefasicN+ /disabledsata-port@0`@' sata-phym | spi@fe2b0000 rockchip,sfc+@:/0Nclk_sfchclk_sfc+ /disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ :  Nbiuciuciu-driveciu-sampleр6defaultDwxyz!(/okay {|}mmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ :Nbiuciuciu-driveciu-sample 6defaultD~!% /disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.A-., Q n6 (:,*+-.Ncorebusaxiblocktimer D6default(kcorebusaxiblocktimer/okay!/>i2s@fe470000rockchip,rk3588-i2s-tdmG:+/(Nmclk_txmclk_rxhclkA)-?11Dtxrx!&k*+ tx-mrx-mX6defaultD/okayportendpointsi2s~i2s@fe480000rockchip,rk3588-i2s-tdmH:y}uNmclk_txmclk_rxhclk?11Dtxrxk^_ tx-mrx-mX6default(D /disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI:Ni2s_clki2s_hclkA?Dtxrx!&6defaultD /disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ:%Ni2s_clki2s_hclkA"?Dtxrx!&6defaultD /disabledinterrupt-controller@fe600000 arm,gic-v3 `h !a8 +msi-controller@fe640000arm,gic-v3-itsdhmsi-controller@fe660000arm,gic-v3-itsfppi-partitionsinterrupt-partition-0interrupt-partition-1 dma-controller@fea10000arm,pl330arm,primecell@ VW:n Napb_pclk1dma-controller@fea30000arm,pl330arm,primecell@ XY:o Napb_pclki2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c:{ Ni2cpclk>D6default+ /disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c:| Ni2cpclk?D6default+/okayregulator@42rockchip,rk8602B7 Tvdd_npu_s0cwdp~+regulator-state-memeeprom@50belling,bl24c16aatmel,24c16Pi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c:} Ni2cpclk@D6default+/okayi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c:~ Ni2cpclkAD6default+ /disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c: Ni2cpclkBD6default+/okaytimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !:TW Npclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt:dc Ntclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF:Nspiclkapb_pclk?11Dtxrx D6default+ /disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG:Nspiclkapb_pclk?11Dtxrx D6default+ /disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH:Nspiclkapb_pclk?DtxrxD6default+/okayAQ pmic@0rockchip,rk806 {6defaultD B@ + + *+ 6+ B+ N+ Z+ f+ r+ ~+  +   +  dvs1-null-pins gpio_pwrctrl2 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1 Tvdd_gpu_s0wdp~0 regulator-state-memdcdc-reg2Tvdd_cpu_lit_s0cwdp~0 regulator-state-memdcdc-reg3 Tvdd_log_s0cw L q0regulator-state-mem  qdcdc-reg4 Tvdd_vdenc_s0cwdp~0regulator-state-memdcdc-reg5 Tvdd_ddr_s0cw L 0regulator-state-mem  Pdcdc-reg6 Tvdd2_ddr_s3cwregulator-state-mem -dcdc-reg7Tvdd_2v0_pldo_s3cw0regulator-state-mem - dcdc-reg8 Tvcc_3v3_s3cw2Z2Zregulator-state-mem - 2Zdcdc-reg9 Tvddq_ddr_s0cwregulator-state-memdcdc-reg10 Tvcc_1v8_s3cww@w@regulator-state-mem - w@pldo-reg1 Tavcc_1v8_s0cww@w@regulator-state-mempldo-reg2 Tvcc_1v8_s0cww@w@regulator-state-mem w@pldo-reg3 Tavdd_1v2_s0cwOOregulator-state-mempldo-reg4 Tvcc_3v3_s0cw2Z2Z0|regulator-state-mempldo-reg5 Tvccio_sd_s0cww@2Z0}regulator-state-mempldo-reg6 Tpldo6_s3cww@w@regulator-state-mem - w@nldo-reg1 Tvdd_0v75_s3cw q qregulator-state-mem -  qnldo-reg2Tvdd_ddr_pll_s0cw P Pregulator-state-mem  Pnldo-reg3 Tavdd_0v75_s0cw q qregulator-state-memnldo-reg4 Tvdd_0v85_s0cw P Pregulator-state-memnldo-reg5 Tvdd_0v75_s0cw q qregulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI:Nspiclkapb_pclk?Dtxrx D6default+ /disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL:Nbaudclkapb_pclk?11 DtxrxD6defaultXN /disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM:Nbaudclkapb_pclk?1 1 DtxrxD6defaultXN/okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN:Nbaudclkapb_pclk?1 1 DtxrxD6defaultXN /disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO:Nbaudclkapb_pclk? DtxrxD6defaultXN /disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP:Nbaudclkapb_pclk? DtxrxD6defaultXN /disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ:Nbaudclkapb_pclk? DtxrxD6defaultXN /disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR:Nbaudclkapb_pclk?ffDtxrxD6defaultXN /disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS:Nbaudclkapb_pclk?f f DtxrxD6defaultXN /disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT:Nbaudclkapb_pclk?f f DtxrxD6defaultXN /disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm:LK NpwmpclkD6defaulte /disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm:LK NpwmpclkD6defaulte /disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm :LK NpwmpclkD6defaulte /disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0:LK NpwmpclkD6defaulte /disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm:ON NpwmpclkD6defaulte /disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm:ON NpwmpclkD6defaulte /disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm :ON NpwmpclkD6defaulte /disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0:ON NpwmpclkD6defaulte /disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm:RQ NpwmpclkD6defaulte /disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm:RQ NpwmpclkD6defaulte /disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm :RQ NpwmpclkD6defaulte /disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0:RQ NpwmpclkD6defaulte /disabledtsadc@fec00000rockchip,rk3588-tsadc:Ntsadcapb_pclkAQkVWtsadc-apbtsadc E \ sD  6gpiootpout  /disabledadc@fec10000rockchip,rk3588-saradc :Nsaradcapb_pclkkU saradc-apb/okay i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c: Ni2cpclkCD6default+ /disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c: Ni2cpclkDD6default+/okayaudio-codec@11everest,es8316:1NmclkA1Qportendpointi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c: Ni2cpclkED6default+ /disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ:Nspiclkapb_pclk?f fDtxrx D6default+ /disabledefuse@fecc0000rockchip,rk3588-otp :Notpapb_pclkphyarbk otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[:p Napb_pclkfphy@fee00000rockchip,rk3588-naneng-combphy:vW NrefapbpipeAQk<Cphyapb )  /disabledjphy@fee20000rockchip,rk3588-naneng-combphy:xW NrefapbpipeAQk>Ephyapb ) /okay'sram@ff001000 mmio-sram +pinctrlrockchip,rk3588-pinctrl *+gpio@fd8a0000rockchip,gpio-bank:qr  ! {gpio@fec20000rockchip,gpio-bank:st  ! gpio@fec30000rockchip,gpio-bank:uv  @ ! gpio@fec40000rockchip,gpio-bank:wx  ` ! vgpio@fec50000rockchip,gpio-bank:yz  ! pcfg-pull-up pcfg-pull-down pcfg-pull-none !pcfg-pull-none-drv-level-2 ! .pcfg-pull-up-drv-level-1  .pcfg-pull-up-drv-level-2  .pcfg-pull-none-smt ! =pcfg-output-high Rauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout ^emmc-bus8 ^emmc-clk ^emmc-cmd ^emmc-data-strobe ^eth1fspigmac1gmac1-miim ^pgmac1-rx-bus20 ^ rgmac1-tx-bus20 ^   qgmac1-rgmii-clk ^sgmac1-rgmii-bus@ ^tgpuhdmii2c0i2c0m2-xfer ^*i2c1i2c1m0-xfer ^  i2c2i2c2m0-xfer ^  i2c3i2c3m0-xfer ^  i2c4i2c4m0-xfer ^  i2c5i2c5m2-xfer ^  i2c6i2c6m0-xfer ^  i2c7i2c7m0-xfer ^  i2c8i2c8m0-xfer ^  i2s0i2s0-lrck ^i2s0-mclk ^i2s0-sclk ^i2s0-sdi0 ^i2s0-sdo0 ^i2s1i2s1m0-lrck ^i2s1m0-sclk ^i2s1m0-sdi0 ^i2s1m0-sdi1 ^i2s1m0-sdi2 ^i2s1m0-sdi3 ^i2s1m0-sdo0 ^ i2s1m0-sdo1 ^ i2s1m0-sdo2 ^ i2s1m0-sdo3 ^ i2s2i2s2m1-lrck ^i2s2m1-sclk ^ i2s2m1-sdi ^ i2s2m1-sdo ^ i2s3i2s3-lrck ^i2s3-sclk ^i2s3-sdi ^i2s3-sdo ^jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp ^pmupwm0pwm0m0-pins ^3pwm1pwm1m0-pins ^4pwm2pwm2m0-pins ^5pwm3pwm3m1-pins ^ 6pwm4pwm4m0-pins ^ pwm5pwm5m0-pins ^ pwm6pwm6m0-pins ^ pwm7pwm7m0-pins ^ pwm8pwm8m0-pins ^ pwm9pwm9m0-pins ^ pwm10pwm10m0-pins ^ pwm11pwm11m0-pins ^ pwm12pwm12m0-pins ^ pwm13pwm13m0-pins ^ pwm14pwm14m0-pins ^ pwm15pwm15m0-pins ^ refclksatasata0sata1sata2sdiosdiom1-pins` ^~sdmmcsdmmc-bus4@ ^zsdmmc-clk ^wsdmmc-cmd ^xsdmmc-det ^yspdif0spdif1spi0spi0m0-pins0 ^spi0m0-cs0 ^spi0m0-cs1 ^spi1spi1m1-pins0 ^spi1m1-cs0 ^spi1m1-cs1 ^spi2spi2m2-pins0 ^ spi2m2-cs0 ^ spi3spi3m1-pins0 ^ spi3m1-cs0 ^spi3m1-cs1 ^spi4spi4m0-pins0 ^spi4m0-cs0 ^spi4m0-cs1 ^tsadctsadc-shut ^uart0uart0m1-xfer ^ 2uart1uart1m1-xfer ^  uart2uart2m0-xfer ^ uart3uart3m1-xfer ^  uart4uart4m1-xfer ^  uart5uart5m1-xfer ^  uart6uart6m1-xfer ^  uart7uart7m1-xfer ^  uart8uart8m1-xfer ^  uart9uart9m1-xfer ^  vopbt656gpio-functsadc-gpio-func ^ledsio-led ^powervcc-5v0-en ^rtl8211frtl8211f-rst ^uusbvcc5v0-host-en ^ wifibtwl-reset ^ wl-dis ^!wl-wake-host ^"bt-dis ^#bt-wake-host ^$video-codec@fdc70000rockchip,rk3588-av1-vpulvdpuAACQׄׄ:AC Naclkhclk! kanalog-soundaudio-graph-card lrk3588-es8316) rMicrophoneMic JackHeadphoneHeadphones. zMIC2Mic JackHeadphonesHPOLHeadphonesHPOR chosen serial2:1500000n8leds gpio-leds6defaultDio-led  status v heartbeatpwm-fanpwm-fan _  Pvcc12v-dcin-regulatorregulator-fixed Tvcc12v_dcincwvcc5v0-host-regulatorregulator-fixed Tvcc5v0_hostwcLK@LK@  6defaultD+(vcc5v0-sys-regulatorregulator-fixed Tvcc5v0_syscwLK@LK@+vcc-5v0-regulatorregulator-fixedTvcc_5v0LK@LK@wc  6defaultD+vcc-1v1-nldo-s3-regulatorregulator-fixedTvcc_1v1_nldo_s3cw+ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesportsinterrupt-namesrangesphysphy-namespower-domainsstatuspinctrl-namespinctrl-0clock-namesdr_modephy_typeresetssnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirkreset-names#phy-cellsphy-supplyrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmu#iommu-cellsdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modetx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlydai-formatmclk-fsremote-endpointmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellspagesizenum-csspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplybitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highrockchip,pinslabelwidgetsroutingdaisstdout-pathcolorlinux,default-triggercooling-levelsfan-supplypwmsenable-active-highgpio