8( $xunlong,orangepi-5rockchip,rk3588s +7Xunlong Orange Pi 5aliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/ethernet@fe1c0000/mmc@fe2c0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55psci"5 < L0,a q~@@  cpu@100cpuarm,cortex-a55psci"5 a q~@@ cpu@200cpuarm,cortex-a55psci"5 a q~@@ cpu@300cpuarm,cortex-a55psci"5 a q~@@ cpu@400cpuarm,cortex-a76psci"5 < L0,a q~@@cpu@500cpuarm,cortex-a76psci"5 a q~@@cpu@600cpuarm,cortex-a76psci"5 < L0,a q~@@cpu@700cpuarm,cortex-a76psci"5 a q~@@ idle-statespscicpu-sleeparm,idle-state#4Kd\xl l2-cache-l0caches@} l2-cache-l1caches@}l2-cache-l2caches@}l2-cache-l3caches@}l2-cache-b0caches@}l2-cache-b1caches@}l2-cache-b2caches@}l2-cache-b3caches@}l3-cachecaches0@}firmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splldisplay-subsystemrockchip,display-subsystemtimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmemusb@fc800000"rockchip,rk3588-ehcigeneric-ehci5 usb*okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci5 usb*okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci5  !usb*okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci5  !usb*okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(5jihkr&1ref_clksuspend_clkbus_clkutmipipe=host " usb3-phy Eutmi_wideN4Um*okaysyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXgsyscon@fd58c000rockchip,rk3588-sys-grfsysconX'syscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ (syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ)syscon@fd5b0000rockchip,rk3588-php-grfsyscon[#syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@8000rockchip,rk3588-usb2phyNophyapb51phyclk usb480m_phy2*okayhost-port*okaysyscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@c000rockchip,rk3588-usb2phyNp phyapb51phyclk usb480m_phy3*okay host-port*okay!syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|<]q@LA.2Fq)׫ׄe/ׄ eZ р #i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=5ts 1i2cpclk$default+*okayregulator@42rockchip,rk8602B'Dvdd_cpu_big0_s0Sgydp%regulator-state-memregulator@43 rockchip,rk8603rockchip,rk8602C'Dvdd_cpu_big1_s0Sgydp%regulator-state-memvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut85]\abcd[71aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop&'()* *disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~5]\ 1aclkiface" *disabled&serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK51baudclkapb_pclk/++4txrx,default>H *disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5 1pwmpclk-defaultU *disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5 1pwmpclk.defaultU *disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5 1pwmpclk/defaultU *disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05 1pwmpclk0defaultU *disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd*power-controller!rockchip,rk3588-power-controller`+*okaypower-domain@8`+power-domain@9  5!#" t123`+power-domain@10 5!#"t4`power-domain@11 5!#"t5`power-domain@12 5t6789`power-domain@13 +`power-domain@14(5t:`power-domain@15 5t;`power-domain@165 t<=>+`power-domain@17 5 t?@A`power-domain@215 tBCDEFGHI+`power-domain@235CAtJ`power-domain@14 5t:`power-domain@155t;`power-domain@225tK`power-domain@245[Z]tLM+`power-domain@2585ZtN`power-domain@2685QtOP`power-domain@2705tQRST+`power-domain@28 5tUV`power-domain@29(5tWX`power-domain@305z{tY`power-domain@31@5WtZ[\]`power-domain@33!5WZ[`power-domain@34"5WZ[`power-domain@37%52t^`power-domain@38&545`power-domain@40(t_`i2s@fddc0000rockchip,rk3588-i2s-tdm51mclk_txmclk_rxhclk<{/`4txNtx-m *disabledi2s@fddf0000rockchip,rk3588-i2s-tdm54451mclk_txmclk_rxhclk<1{/`4txNtx-m *disabledi2s@fddfc000rockchip,rk3588-i2s-tdm500,1mclk_txmclk_rxhclk<-{/`4rxNrx-m *disabledqos@fdf35000rockchip,rk3588-qossysconP 6qos@fdf35200rockchip,rk3588-qossysconR 7qos@fdf35400rockchip,rk3588-qossysconT 8qos@fdf35600rockchip,rk3588-qossysconV 9qos@fdf36000rockchip,rk3588-qossyscon` Yqos@fdf39000rockchip,rk3588-qossyscon ^qos@fdf3d800rockchip,rk3588-qossyscon _qos@fdf3e000rockchip,rk3588-qossyscon [qos@fdf3e200rockchip,rk3588-qossyscon Zqos@fdf3e400rockchip,rk3588-qossyscon \qos@fdf3e600rockchip,rk3588-qossyscon ]qos@fdf40000rockchip,rk3588-qossyscon Wqos@fdf40200rockchip,rk3588-qossyscon Xqos@fdf40400rockchip,rk3588-qossyscon Qqos@fdf40500rockchip,rk3588-qossyscon Rqos@fdf40600rockchip,rk3588-qossyscon Sqos@fdf40800rockchip,rk3588-qossyscon Tqos@fdf41000rockchip,rk3588-qossyscon Uqos@fdf41100rockchip,rk3588-qossyscon Vqos@fdf60000rockchip,rk3588-qossyscon <qos@fdf60200rockchip,rk3588-qossyscon =qos@fdf60400rockchip,rk3588-qossyscon >qos@fdf61000rockchip,rk3588-qossyscon ?qos@fdf61200rockchip,rk3588-qossyscon @qos@fdf61400rockchip,rk3588-qossyscon Aqos@fdf62000rockchip,rk3588-qossyscon :qos@fdf63000rockchip,rk3588-qossyscon0 ;qos@fdf64000rockchip,rk3588-qossyscon@ Jqos@fdf66000rockchip,rk3588-qossyscon` Bqos@fdf66200rockchip,rk3588-qossysconb Cqos@fdf66400rockchip,rk3588-qossyscond Dqos@fdf66600rockchip,rk3588-qossysconf Eqos@fdf66800rockchip,rk3588-qossysconh Fqos@fdf66a00rockchip,rk3588-qossysconj Gqos@fdf66c00rockchip,rk3588-qossysconl Hqos@fdf66e00rockchip,rk3588-qossysconn Iqos@fdf67000rockchip,rk3588-qossysconp Kqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 4qos@fdf71000rockchip,rk3588-qossyscon 5qos@fdf72000rockchip,rk3588-qossyscon 1qos@fdf72200rockchip,rk3588-qossyscon" 2qos@fdf72400rockchip,rk3588-qossyscon$ 3qos@fdf80000rockchip,rk3588-qossyscon Nqos@fdf81000rockchip,rk3588-qossyscon Oqos@fdf81200rockchip,rk3588-qossyscon Pqos@fdf82000rockchip,rk3588-qossyscon Lqos@fdf82200rockchip,rk3588-qossyscon" Mpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?05CH>MR)1aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`aaaa0b0 " pcie-phy"T @ @0 @@dbiapbconfigN). pwrpipe+ *disabledlegacy-interrupt-controller apcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O05DI?NSs)1aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`cccc@b@ d pcie-phy"T @ @0 A@dbiapbconfigN*/ pwrpipe+*okay &e2flegacy-interrupt-controller cdfi@fe060000rockchip,rk3588-dfi@&0:gethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(567Y^501stmmacethclk_mac_refpclk_macaclk_macptp_ref!N$ stmmaceth'B#Shctij*okayoutputk rgmii-rxidlmnopdefaultBmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22N  &e kstmmac-axi-config hrx-queues-configiqueue0queue1tx-queues-config/jqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(5b_eTo1satapmaliverxoobrefasicE+ *disabledsata-port@0W@ d sata-phyd s sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(5dagVq1satapmaliverxoobrefasicE+ *disabledsata-port@0W@ " sata-phyd s spi@fe2b0000 rockchip,sfc+@5/01clk_sfchclk_sfc+*okaydefaultqflash@0jedec,spi-normmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ 5  1biuciuciu-driveciu-sampleрdefaultrstu(*okayvwmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ 51biuciuciu-driveciu-sample defaultx% *disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.<-., L n6 (5,*+-.1corebusaxiblocktimer yz{|}default(Ncorebusaxiblocktimer *disabledi2s@fe470000rockchip,rk3588-i2s-tdmG5+/(1mclk_txmclk_rxhclk<)-{/++4txrx&N*+ tx-mrx-mdefault(~ *disabledi2s@fe480000rockchip,rk3588-i2s-tdmH5y}u1mclk_txmclk_rxhclk/++4txrxN^_ tx-mrx-mdefault( *disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI51i2s_clki2s_hclk<{/4txrx&default *disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ5%1i2s_clki2s_hclk<"{/4txrx&default *disabledinterrupt-controller@fe600000 arm,gic-v3 `h .a88C+msi-controller@fe640000arm,gic-v3-itsdCRbmsi-controller@fe660000arm,gic-v3-itsfCRppi-partitionsinterrupt-partition-0]interrupt-partition-1] dma-controller@fea10000arm,pl330arm,primecell@ VWf5n 1apb_pclk}+dma-controller@fea30000arm,pl330arm,primecell@ XYf5o 1apb_pclk}i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c5{ 1i2cpclk>default+ *disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c5| 1i2cpclk?default+*okayregulator@42rockchip,rk8602B' Dvdd_npu_s0Sgydp~%regulator-state-memi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c5} 1i2cpclk@default+ *disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c5~ 1i2cpclkAdefault+ *disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c5 1i2cpclkBdefault+ *disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !5TW 1pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt5dc 1tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF51spiclkapb_pclk/++4txrx default+ *disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG51spiclkapb_pclk/++4txrx default+ *disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH51spiclkapb_pclk/4txrxdefault+*okay<L pmic@0rockchip,rk806 defaultB@%%%%%%%% % %  -% : G T% ` pdvs1-null-pins |gpio_pwrctrl2 pin_fun0dvs2-null-pins |gpio_pwrctrl2 pin_fun0dvs3-null-pins |gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1 Dvdd_gpu_s0gydp~0 regulator-state-memdcdc-reg2Dvdd_cpu_lit_s0Sgydp~0 regulator-state-memdcdc-reg3 Dvdd_log_s0Sgy L q0regulator-state-mem qdcdc-reg4 Dvdd_vdenc_s0Sgydp~0regulator-state-memdcdc-reg5 Dvdd_ddr_s0Sgy L 0regulator-state-mem Pdcdc-reg6 Dvdd2_ddr_s3Sgyregulator-state-mem dcdc-reg7Dvdd_2v0_pldo_s3Sgy0regulator-state-mem  dcdc-reg8 Dvcc_3v3_s3Sgy2Z2Zregulator-state-mem  2Zdcdc-reg9 Dvddq_ddr_s0Sgregulator-state-memdcdc-reg10 Dvcc_1v8_s3Sgyw@w@regulator-state-mem  w@pldo-reg1 Davcc_1v8_s0Sgyw@w@regulator-state-mempldo-reg2 Dvcc_1v8_s0Sgyw@w@regulator-state-mem w@pldo-reg3 Davdd_1v2_s0SgyOOregulator-state-mempldo-reg4 Dvcc_3v3_s0Sgy2Z2Z0regulator-state-mempldo-reg5 Dvccio_sd_s0Sgyw@2Z0wregulator-state-mempldo-reg6 Dpldo6_s3Sgyw@w@regulator-state-mem  w@nldo-reg1 Dvdd_0v75_s3Sgy q qregulator-state-mem  qnldo-reg2Dvdd_ddr_pll_s0Sgy P Pregulator-state-mem Pnldo-reg3 Davdd_0v75_s0Sgy q qregulator-state-memnldo-reg4 Dvdd_0v85_s0Sgy P Pregulator-state-memnldo-reg5 Dvdd_0v75_s0Sgy q qregulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI51spiclkapb_pclk/4txrx default+ *disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL51baudclkapb_pclk/++ 4txrxdefaultH> *disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM51baudclkapb_pclk/+ + 4txrxdefaultH>*okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN51baudclkapb_pclk/+ + 4txrxdefaultH> *disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO51baudclkapb_pclk/ 4txrxdefaultH> *disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP51baudclkapb_pclk/ 4txrxdefaultH> *disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ51baudclkapb_pclk/ 4txrxdefaultH> *disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR51baudclkapb_pclk/``4txrxdefaultH> *disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS51baudclkapb_pclk/` ` 4txrxdefaultH> *disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT51baudclkapb_pclk/` ` 4txrxdefaultH> *disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5LK 1pwmpclkdefaultU *disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5LK 1pwmpclkdefaultU *disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5LK 1pwmpclkdefaultU *disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05LK 1pwmpclkdefaultU *disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5ON 1pwmpclkdefaultU *disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5ON 1pwmpclkdefaultU *disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5ON 1pwmpclkdefaultU *disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05ON 1pwmpclkdefaultU *disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5RQ 1pwmpclkdefaultU *disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5RQ 1pwmpclkdefaultU *disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5RQ 1pwmpclkdefaultU *disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05RQ 1pwmpclkdefaultU *disabledtsadc@fec00000rockchip,rk3588-tsadc51tsadcapb_pclk<LNVWtsadc-apbtsadc    # gpiootpout -*okayadc@fec10000rockchip,rk3588-saradc C51saradcapb_pclkNU saradc-apb*okay Ui2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c5 1i2cpclkCdefault+*okayrtc@51haoyu,hym8563Qhym8563default  ai2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c5 1i2cpclkDdefault+ *disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c5 1i2cpclkEdefault+ *disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ51spiclkapb_pclk/` `4txrx default+ *disabledefuse@fecc0000rockchip,rk3588-otp 51otpapb_pclkphyarbN otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c onpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[f5p 1apb_pclk}`phy@fee00000rockchip,rk3588-naneng-combphy5vW 1refapbpipe<LN<Cphyapb t# *okaydphy@fee20000rockchip,rk3588-naneng-combphy5xW 1refapbpipe<LN>Ephyapb t# *okay"sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl+gpio@fd8a0000rockchip,gpio-bank5qr `  pgpio@fec20000rockchip,gpio-bank5st `  pgpio@fec30000rockchip,gpio-bank5uv ` @  pgpio@fec40000rockchip,gpio-bank5wx ` `  pegpio@fec50000rockchip,gpio-bank5yz `  ppcfg-pull-up pcfg-pull-down pcfg-pull-none pcfg-pull-none-drv-level-2  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout yemmc-bus8 zemmc-clk {emmc-cmd |emmc-data-strobe }eth1fspifspim0-pins` qgmac1gmac1-miim lgmac1-rx-bus20  ngmac1-tx-bus20    mgmac1-rgmii-clk ogmac1-rgmii-bus@ pgpuhdmii2c0i2c0m2-xfer $i2c1i2c1m0-xfer  i2c2i2c2m0-xfer   i2c3i2c3m0-xfer   i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2c6i2c6m3-xfer   i2c7i2c7m0-xfer   i2c8i2c8m0-xfer   i2s0i2s0-lrck ~i2s0-sclk i2s0-sdi0 i2s0-sdi1 i2s0-sdi2 i2s0-sdi3 i2s0-sdo0 i2s0-sdo1 i2s0-sdo2 i2s0-sdo3 i2s1i2s1m0-lrck i2s1m0-sclk i2s1m0-sdi0 i2s1m0-sdi1 i2s1m0-sdi2 i2s1m0-sdi3 i2s1m0-sdo0  i2s1m0-sdo1  i2s1m0-sdo2  i2s1m0-sdo3  i2s2i2s2m1-lrck i2s2m1-sclk  i2s2m1-sdi  i2s2m1-sdo  i2s3i2s3-lrck i2s3-sclk i2s3-sdi i2s3-sdo jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp pmupwm0pwm0m0-pins -pwm1pwm1m0-pins .pwm2pwm2m0-pins /pwm3pwm3m0-pins 0pwm4pwm4m0-pins  pwm5pwm5m0-pins pwm6pwm6m0-pins  pwm7pwm7m0-pins  pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins  pwm12pwm12m0-pins  pwm13pwm13m0-pins  pwm14pwm14m0-pins  pwm15pwm15m0-pins  refclksatasata0sata1sata2sdiosdiom1-pins` xsdmmcsdmmc-bus4@ usdmmc-clk rsdmmc-cmd ssdmmc-det tspdif0spdif1spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m1-pins0 spi1m1-cs0 spi1m1-cs1 spi2spi2m2-pins0  spi2m2-cs0 spi3spi3m1-pins0  spi3m1-cs0 spi3m1-cs1 spi4spi4m0-pins0 spi4m0-cs0 spi4m0-cs1 tsadctsadc-shut uart0uart0m1-xfer  ,uart1uart1m1-xfer   uart2uart2m0-xfer  uart3uart3m1-xfer   uart4uart4m1-xfer   uart5uart5m1-xfer   uart6uart6m1-xfer   uart7uart7m1-xfer   uart8uart8m1-xfer   uart9uart9m1-xfer   vopbt656gpio-functsadc-gpio-func leds-gpio hym8563hym8563-int usb-typecusbc0-int typec5v-pwren video-codec@fdc70000rockchip,rk3588-av1-vpulvdpu<ACLׄׄ5AC 1aclkhclk Nchosen serial2:1500000n8adc-keys adc-keys  buttons ,w@ Fdbutton-recovery TRecovery Zh eleds gpio-ledsdefaultled-1 , Tstatus_led heartbeatvbus-typec-regulatorregulator-fixed  edefault Dvbus_typecyLK@LK@%vcc5v0-sys-regulatorregulator-fixed Dvcc5v0_sysSgyLK@LK@%vcc-3v3-sd-s0-regulatorregulator-fixed  , Dvcc_3v3_sd_s0gy2Z2Zvvcc3v3-pcie20-regulatorregulator-fixed  ,Dvcc3v3_pcie20gyw@w@ P%f compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesportsinterrupt-namesrangesphysphy-namespower-domainsstatusclock-namesdr_modephy_typeresetssnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirkreset-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmu#iommu-cellsdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerreset-gpiosvpcie3v3-supplyrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modetx_delayreset-assert-usreset-deassert-ussnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthfifo-depthcap-sd-highspeeddisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyrockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-cssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplywakeup-sourcebitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltlinux,default-triggerenable-active-highgpioenable-active-lowstartup-delay-us