8( Y(xunlong,orangepi-5-plusrockchip,rk3588 +7Xunlong Orange Pi 5 Plusaliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000/mmc@fe2c0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55 psci0 7 G0,\ ly@@   cpu@100cpuarm,cortex-a55 psci0 \ ly@@  cpu@200cpuarm,cortex-a55 psci0 \ ly@@  cpu@300cpuarm,cortex-a55 psci0 \ ly@@  cpu@400cpuarm,cortex-a76 psci0 7 G0,\ ly@@ cpu@500cpuarm,cortex-a76 psci0 \ ly@@ cpu@600cpuarm,cortex-a76 psci0 7 G0,\ ly@@ cpu@700cpuarm,cortex-a76 psci0 \ ly@@ idle-statespscicpu-sleeparm,idle-state/FdWxg l2-cache-l0cachen{@x l2-cache-l1cachen{@x l2-cache-l2cachen{@x l2-cache-l3cachen{@x l2-cache-b0cachen{@x l2-cache-b1cachen{@x l2-cache-b2cachen{@x l2-cache-b3cachen{@x l3-cachecachen0{@x firmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14  protocol@16 pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splldisplay-subsystemrockchip,display-subsystemtimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram +sram@0arm,scmi-shmem  usb@fc800000"rockchip,rk3588-ehcigeneric-ehci 0 usb%okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci 0 usb%okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci 0 ! usb%okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci 0 ! usb%okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3 @(0jihkr&,ref_clksuspend_clkbus_clkutmipipe8host"  usb3-phy @utmi_wideI4Ph %disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfd X isyscon@fd58c000rockchip,rk3588-sys-grfsyscon X (syscon@fd5a4000rockchip,rk3588-vop-grfsyscon Z@  )syscon@fd5a8000rockchip,rk3588-vo-grfsyscon Z *syscon@fd5b0000rockchip,rk3588-php-grfsyscon [ $syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon [ syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon \@ syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@+usb2-phy@8000rockchip,rk3588-usb2phy Iophyapb0,phyclk usb480m_phy2%okay host-port%okay# syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@+usb2-phy@c000rockchip,rk3588-usb2phy Ip phyapb0,phyclk usb480m_phy3%okay host-port%okay# !syscon@fd5f0000rockchip,rk3588-iocsyscon _ sram@fd600000 mmio-sram ``+clock-controller@fd7c0000rockchip,rk3588-cru |7]q@GA.2Fq)׫ׄe/ׄ eZ р $ i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c =0ts ,i2cpclk%default+%okayregulator@42rockchip,rk8602 B-Jvdd_cpu_big0_s0Ymdp& regulator-state-memregulator@43 rockchip,rk8603rockchip,rk8602 C-Jvdd_cpu_big1_s0Ymdp& regulator-state-memvop@fdd90000rockchip,rk3588-vop  BPvopgamma-lut80]\abcd[7,aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop'() *+ %disabledports+ port@0+ port@1+ port@2+ port@3+ iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu  ~0]\ ,aclkiface( %disabled 'serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uart K0,baudclkapb_pclk5,,:txrx-defaultDN %disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 ,pwmpclk.default[ %disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 ,pwmpclk/default[ %disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 ,pwmpclk0default[%okay pwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00 ,pwmpclk1default[%okay power-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd  +power-controller!rockchip,rk3588-power-controllerf+%okay power-domain@8 f+power-domain@9  0!#" z234f+power-domain@10 0!#"z5fpower-domain@11 0!#"z6fpower-domain@12 0z789:fpower-domain@13 +fpower-domain@14 (0z;fpower-domain@15  0z<fpower-domain@16 0 z=>?+fpower-domain@17  0 z@ABfpower-domain@21 0 zCDEFGHIJ+fpower-domain@23 0CAzKfpower-domain@14  0z;fpower-domain@15 0z<fpower-domain@22 0zLfpower-domain@24 0[Z]zMN+fpower-domain@25 80ZzOfpower-domain@26 80QzPQfpower-domain@27 00zRSTU+fpower-domain@28  0zVWfpower-domain@29 (0zXYfpower-domain@30 0z{zZfpower-domain@31 @0Wz[\]^fpower-domain@33 !0WZ[fpower-domain@34 "0WZ[fpower-domain@37 %02z_fpower-domain@38 &045fpower-domain@40 (z`fi2s@fddc0000rockchip,rk3588-i2s-tdm 0,mclk_txmclk_rxhclk75a:txItx-m %disabledi2s@fddf0000rockchip,rk3588-i2s-tdm 0445,mclk_txmclk_rxhclk715a:txItx-m %disabledi2s@fddfc000rockchip,rk3588-i2s-tdm 000,,mclk_txmclk_rxhclk7-5a:rxIrx-m %disabledqos@fdf35000rockchip,rk3588-qossyscon P  7qos@fdf35200rockchip,rk3588-qossyscon R  8qos@fdf35400rockchip,rk3588-qossyscon T  9qos@fdf35600rockchip,rk3588-qossyscon V  :qos@fdf36000rockchip,rk3588-qossyscon `  Zqos@fdf39000rockchip,rk3588-qossyscon  _qos@fdf3d800rockchip,rk3588-qossyscon  `qos@fdf3e000rockchip,rk3588-qossyscon  \qos@fdf3e200rockchip,rk3588-qossyscon  [qos@fdf3e400rockchip,rk3588-qossyscon  ]qos@fdf3e600rockchip,rk3588-qossyscon  ^qos@fdf40000rockchip,rk3588-qossyscon  Xqos@fdf40200rockchip,rk3588-qossyscon   Yqos@fdf40400rockchip,rk3588-qossyscon   Rqos@fdf40500rockchip,rk3588-qossyscon   Sqos@fdf40600rockchip,rk3588-qossyscon   Tqos@fdf40800rockchip,rk3588-qossyscon   Uqos@fdf41000rockchip,rk3588-qossyscon   Vqos@fdf41100rockchip,rk3588-qossyscon   Wqos@fdf60000rockchip,rk3588-qossyscon  =qos@fdf60200rockchip,rk3588-qossyscon   >qos@fdf60400rockchip,rk3588-qossyscon   ?qos@fdf61000rockchip,rk3588-qossyscon   @qos@fdf61200rockchip,rk3588-qossyscon   Aqos@fdf61400rockchip,rk3588-qossyscon   Bqos@fdf62000rockchip,rk3588-qossyscon  ;qos@fdf63000rockchip,rk3588-qossyscon 0  <qos@fdf64000rockchip,rk3588-qossyscon @  Kqos@fdf66000rockchip,rk3588-qossyscon `  Cqos@fdf66200rockchip,rk3588-qossyscon b  Dqos@fdf66400rockchip,rk3588-qossyscon d  Eqos@fdf66600rockchip,rk3588-qossyscon f  Fqos@fdf66800rockchip,rk3588-qossyscon h  Gqos@fdf66a00rockchip,rk3588-qossyscon j  Hqos@fdf66c00rockchip,rk3588-qossyscon l  Iqos@fdf66e00rockchip,rk3588-qossyscon n  Jqos@fdf67000rockchip,rk3588-qossyscon p  Lqos@fdf67200rockchip,rk3588-qossyscon r qos@fdf70000rockchip,rk3588-qossyscon  5qos@fdf71000rockchip,rk3588-qossyscon   6qos@fdf72000rockchip,rk3588-qossyscon  2qos@fdf72200rockchip,rk3588-qossyscon "  3qos@fdf72400rockchip,rk3588-qossyscon $  4qos@fdf80000rockchip,rk3588-qossyscon  Oqos@fdf81000rockchip,rk3588-qossyscon   Pqos@fdf81200rockchip,rk3588-qossyscon   Qqos@fdf82000rockchip,rk3588-qossyscon  Mqos@fdf82200rockchip,rk3588-qossyscon "  Npcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?00CH>MR),aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`bbbb0c0 "  pcie-phy"T @ @0 @@dbiapbconfigI). pwrpipe+%okay d #elegacy-interrupt-controller3  bpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O00DI?NSs),aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`ffff@c@ g  pcie-phy"T @ @0 A@dbiapbconfigI*/ pwrpipe+%okay h#elegacy-interrupt-controller3  fdfi@fe060000 rockchip,rk3588-dfi@&0:iethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a  macirqeth_wake_irq(067Y^50,stmmacethclk_mac_refpclk_macaclk_macptp_ref!I$ stmmaceth(H$Yjizkl %disabledmdiosnps,dwmac-mdio+stmmac-axi-config jrx-queues-config kqueue0queue1tx-queues-config lqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci !(0b_eTo,satapmaliverxoobrefasic+ %disabledsata-port@0 @g  sata-phy - sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci #(0dagVq,satapmaliverxoobrefasic+ %disabledsata-port@0 @"  sata-phy - spi@fe2b0000 rockchip,sfc +@0/0,clk_sfchclk_sfc+%okaydefaultmflash@0jedec,spi-nor <N_mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc ,@ 0  ,biuciuciu-driveciu-samplep@рdefaultnopq(%okayU{ rstmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc -@ 0,biuciuciu-driveciu-samplep@ defaultu% %disabledmmc@fe2e0000rockchip,rk3588-dwcmshc .7-., G n6 (0,*+-.,corebusaxiblocktimer@ vwxyzdefault(Icorebusaxiblocktimer%okayUi2s@fe470000rockchip,rk3588-i2s-tdm G0+/(,mclk_txmclk_rxhclk7)-5,,:txrx&I*+ tx-mrx-mdefault{|}~%okay i2s@fe480000rockchip,rk3588-i2s-tdm H0y}u,mclk_txmclk_rxhclk5,,:txrxI^_ tx-mrx-mdefault( %disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2s I0,i2s_clki2s_hclk75:txrx&default%okayi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2s J0%,i2s_clki2s_hclk7"5:txrx&default %disabledinterrupt-controller@fe600000 arm,gic-v3  `h 3.a88C+ msi-controller@fe640000arm,gic-v3-its dCR cmsi-controller@fe660000arm,gic-v3-its fCR ppi-partitionsinterrupt-partition-0] interrupt-partition-1]  dma-controller@fea10000arm,pl330arm,primecell @ VWf0n ,apb_pclk} ,dma-controller@fea30000arm,pl330arm,primecell @ XYf0o ,apb_pclk} i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c 0{ ,i2cpclk>default+ %disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0| ,i2cpclk?default+ %disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0} ,i2cpclk@default+ %disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0~ ,i2cpclkAdefault+ %disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 ,i2cpclkBdefault+ %disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !0TW ,pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt 0dc ,tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spi F0,spiclkapb_pclk5,,:txrx default+ %disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spi G0,spiclkapb_pclk5,,:txrx default+ %disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spi H0,spiclkapb_pclk5:txrxdefault+%okay7G pmic@0rockchip,rk806  rdefault<B@&&&&&&&& & &  -& : G T& ` pdvs1-null-pins |gpio_pwrctrl1 pin_fun0 dvs2-null-pins |gpio_pwrctrl2 pin_fun0 dvs3-null-pins |gpio_pwrctrl3 pin_fun0 regulatorsdcdc-reg1 Jvdd_gpu_s0m dp~0regulator-state-memdcdc-reg2Jvdd_cpu_lit_s0Ymdp~0 regulator-state-memdcdc-reg3 Jvdd_log_s0Ym L 0regulator-state-mem qdcdc-reg4 Jvdd_vdenc_s0Ymdp 0regulator-state-memdcdc-reg5 Jvdd_ddr_s0Ym L 0regulator-state-mem Pdcdc-reg6 Jvdd2_ddr_s3Ym regulator-state-mem dcdc-reg7Jvdd_2v0_pldo_s3Ym0 regulator-state-mem  dcdc-reg8 Jvcc_3v3_s3Ym2Z2Z sregulator-state-mem  2Zdcdc-reg9 Jvddq_ddr_s0Ymregulator-state-memdcdc-reg10 Jvcc_1v8_s3Ymw@w@regulator-state-mem  w@pldo-reg1 Javcc_1v8_s0Ymw@w@regulator-state-mem w@pldo-reg2 Jvcc_1v8_s0Ymw@w@ regulator-state-mem w@pldo-reg3 Javdd_1v2_s0YmOOregulator-state-mempldo-reg4 Jvcc_3v3_s0Ym2Z2Z0 regulator-state-mempldo-reg5 Jvccio_sd_s0Ymw@2Z0 tregulator-state-mempldo-reg6 Jpldo6_s3Ymw@w@regulator-state-mem  w@nldo-reg1 Jvdd_0v75_s3Ym q qregulator-state-mem  qnldo-reg2Jvdd_ddr_pll_s0Ym P Pregulator-state-mem Pnldo-reg3 Javdd_0v75_s0Ym  regulator-state-memnldo-reg4 Jvdd_0v85_s0Ym P Pregulator-state-memnldo-reg5 Jvdd_0v75_s0Ym q qregulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spi I0,spiclkapb_pclk5:txrx default+ %disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uart L0,baudclkapb_pclk5,, :txrxdefaultND %disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uart M0,baudclkapb_pclk5, , :txrxdefaultND%okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uart N0,baudclkapb_pclk5, , :txrxdefaultND %disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uart O0,baudclkapb_pclk5 :txrxdefaultND %disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uart P0,baudclkapb_pclk5 :txrxdefaultND %disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uart Q0,baudclkapb_pclk5 :txrxdefaultND %disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uart R0,baudclkapb_pclk5aa:txrxdefaultND %disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uart S0,baudclkapb_pclk5a a :txrxdefaultND %disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uart T0,baudclkapb_pclk5a a :txrxdefaultND%okaypwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK ,pwmpclkdefault[ %disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK ,pwmpclkdefault[ %disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK ,pwmpclkdefault[ %disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00LK ,pwmpclkdefault[ %disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON ,pwmpclkdefault[ %disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON ,pwmpclkdefault[ %disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON ,pwmpclkdefault[ %disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00ON ,pwmpclkdefault[ %disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ ,pwmpclkdefault[ %disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ ,pwmpclkdefault[ %disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ ,pwmpclkdefault[ %disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00RQ ,pwmpclkdefault[ %disabledtsadc@fec00000rockchip,rk3588-tsadc 0,tsadcapb_pclk7GIVWtsadc-apbtsadc    # gpiootpout -%okayadc@fec10000rockchip,rk3588-saradc  C0,saradcapb_pclkIU saradc-apb%okay U i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 ,i2cpclkCdefault+%okayrtc@51haoyu,hym8563 Q rhym8563default ai2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 ,i2cpclkDdefault+%okayaudio-codec@11everest,es8388 01,mclk o {  71G i2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 ,i2cpclkEdefault+ %disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spi J0,spiclkapb_pclk5a a:txrx default+ %disabledefuse@fecc0000rockchip,rk3588-otp  0,otpapb_pclkphyarbI otpapbarb+cpu-code@2 id@7 cpu-leakage@17 cpu-leakage@18 cpu-leakage@19 log-leakage@1a gpu-leakage@1b cpu-version@1c  npu-leakage@28 (codec-leakage@29 )dma-controller@fed10000arm,pl330arm,primecell @ Z[f0p ,apb_pclk} aphy@fee00000rockchip,rk3588-naneng-combphy 0vW ,refapbpipe7GI<Cphyapb $ %okay gphy@fee20000rockchip,rk3588-naneng-combphy 0xW ,refapbpipe7GI>Ephyapb $ %okay "sram@ff001000 mmio-sram +pinctrlrockchip,rk3588-pinctrl+ gpio@fd8a0000rockchip,gpio-bank 0qr ` 3 p rgpio@fec20000rockchip,gpio-bank 0st ` 3 p gpio@fec30000rockchip,gpio-bank 0uv ` @ 3 p gpio@fec40000rockchip,gpio-bank 0wx ` ` 3 p dgpio@fec50000rockchip,gpio-bank 0yz ` 3 p hpcfg-pull-up  pcfg-pull-down  pcfg-pull-none  pcfg-pull-none-drv-level-2   pcfg-pull-up-drv-level-1   pcfg-pull-up-drv-level-2   pcfg-pull-none-smt   auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout  vemmc-bus8  wemmc-clk  xemmc-cmd  yemmc-data-strobe  zeth1fspifspim1-pins`     mgmac1gpuhdmii2c0i2c0m2-xfer  %i2c1i2c1m0-xfer    i2c2i2c2m0-xfer    i2c3i2c3m0-xfer    i2c4i2c4m0-xfer    i2c5i2c5m0-xfer    i2c6i2c6m0-xfer    i2c7i2c7m0-xfer    i2c8i2c8m0-xfer    i2s0i2s0-lrck  {i2s0-mclk  |i2s0-sclk  }i2s0-sdi0  ~i2s0-sdo0  i2s1i2s1m0-lrck  i2s1m0-sclk  i2s1m0-sdi0  i2s1m0-sdi1  i2s1m0-sdi2  i2s1m0-sdi3  i2s1m0-sdo0   i2s1m0-sdo1   i2s1m0-sdo2   i2s1m0-sdo3   i2s2i2s2m0-lrck  i2s2m0-sclk  i2s2m0-sdi  i2s2m0-sdo  i2s3i2s3-lrck  i2s3-sclk  i2s3-sdi  i2s3-sdo  jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp  pmupwm0pwm0m0-pins  .pwm1pwm1m0-pins  /pwm2pwm2m1-pins   0pwm3pwm3m1-pins   1pwm4pwm4m0-pins   pwm5pwm5m0-pins   pwm6pwm6m0-pins   pwm7pwm7m0-pins   pwm8pwm8m0-pins   pwm9pwm9m0-pins   pwm10pwm10m0-pins   pwm11pwm11m0-pins   pwm12pwm12m0-pins   pwm13pwm13m0-pins   pwm14pwm14m0-pins   pwm15pwm15m0-pins   refclksatasata0sata1sata2sdiosdiom1-pins`  usdmmcsdmmc-bus4@  qsdmmc-clk  nsdmmc-cmd  osdmmc-det  pspdif0spdif1spi0spi0m0-pins0  spi0m0-cs0  spi0m0-cs1  spi1spi1m1-pins0  spi1m1-cs0  spi1m1-cs1  spi2spi2m2-pins0   spi2m2-cs0   spi3spi3m1-pins0   spi3m1-cs0  spi3m1-cs1  spi4spi4m0-pins0  spi4m0-cs0  spi4m0-cs1  tsadctsadc-shut  uart0uart0m1-xfer   -uart1uart1m1-xfer    uart2uart2m0-xfer   uart3uart3m1-xfer    uart4uart4m1-xfer    uart5uart5m1-xfer    uart6uart6m1-xfer    uart7uart7m1-xfer    uart8uart8m1-xfer    uart9uart9m0-xfer    vopbt656gpio-functsadc-gpio-func  eth0gmac0hym8563hym8563-int  ledsblue-led  ir-receiverir-receiver-pin   soundhp-detect  usbvcc5v0-usb20-en  video-codec@fdc70000rockchip,rk3588-av1-vpu lvdpu7ACGׄׄ0AC ,aclkhclk Isyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon [ syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon \ i2s@fddc8000rockchip,rk3588-i2s-tdm ܀0,mclk_txmclk_rxhclk75a:txItx-m %disabledi2s@fddf4000rockchip,rk3588-i2s-tdm @099?,mclk_txmclk_rxhclk765a:txItx-m %disabledi2s@fddf8000rockchip,rk3588-i2s-tdm ߀0++',mclk_txmclk_rxhclk7(5a:rxIrx-m %disabledi2s@fde00000rockchip,rk3588-i2s-tdm 0&&",mclk_txmclk_rxhclk7#5a:rxIrx-m %disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+00@E;JOt),aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`   pcie-phy"T @ @0 @@dbiapbconfigI&+ pwrpipe%okay h#legacy-interrupt-controller3  pcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+00AF<KPu),aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`   pcie-phy"T @ @@0 @@@dbiapbconfigI', pwrpipe %disabledlegacy-interrupt-controller3  pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /00BG=LQ),aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` c    pcie-phy"T @ @0 @@dbiapbconfigI(- pwrpipe+%okay h#legacy-interrupt-controller3  ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a  macirqeth_wake_irq(067X]40,stmmacethclk_mac_refpclk_macaclk_macptp_ref!I# stmmaceth(H$Yiz %disabledmdiosnps,dwmac-mdio+stmmac-axi-config rx-queues-config queue0queue1tx-queues-config queue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci "(0c`fUp,satapmaliverxoobrefasic+ %disabledsata-port@0 @  sata-phy - phy@fee10000rockchip,rk3588-naneng-combphy 0wW ,refapbpipe7GI=Dphyapb $ %okay phy@fee80000rockchip,rk3588-pcie3-phy 0y,pclkIHphy $ (%okay chosen 9serial2:1500000n8adc-keys-0 adc-keys E Qbuttons bw@ |dbutton-maskrom Mask Rom  adc-keys-1 adc-keys E Qbuttons bw@ |dbutton-recovery Recovery h speaker-audio-amplifiersimple-audio-amplifier d Speaker Amp headphones-audio-amplifiersimple-audio-amplifier d Headphones Amp ir-receivergpio-ir-receiver h defaultgpio-leds gpio-ledsdefaultled  indicator  dpwm-fanpwm-fan FKPd & Ppwm-leds pwm-ledsled  indicator   asoundsimple-audio-carddefault Analog 3 Ni2s g   ^ MicrophoneOnboard MicrophoneMicrophoneMicrophone JackSpeakerSpeakerHeadphoneHeadphonesr HeadphonesLOUT1HeadphonesROUT1SpeakerLOUT2SpeakerROUT2HeadphonesHeadphones Amp OUTLHeadphonesHeadphones Amp OUTRHeadphones Amp INLLOUT1Headphones Amp INRROUT1SpeakerSpeaker Amp OUTLSpeakerSpeaker Amp OUTRSpeaker Amp INLLOUT2Speaker Amp INRROUT2LINPUT1Microphone JackRINPUT1Microphone JackLINPUT2Onboard MicrophoneRINPUT2Onboard Microphonesimple-audio-card,cpu   simple-audio-card,codec  vcc3v3-pcie30-regulatorregulator-fixed 5 Jvcc3v3_pcie302Z2Z H& vcc3v3-pcie-eth-regulatorregulator-fixed d Jvcc3v3_pcie_eth2Z2Z HP& evcc3v3-wf-regulatorregulator-fixed 5  Jvcc3v3_wf2Z2Z HP& vcc5v0-sys-regulatorregulator-fixed Jvcc5v0_sysYmLK@LK@ &vcc5v0-usb20-regulatorregulator-fixed 5 ddefault Jvcc5v0_usb20LK@LK@& # compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesportsinterrupt-namesrangesphysphy-namespower-domainsstatusclock-namesdr_modephy_typeresetssnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirkreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmu#iommu-cellsdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplyinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthfifo-depthcap-sd-highspeedcd-gpiosdisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-cssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplywakeup-sourceAVDD-supplyDVDD-supplyHPVDD-supplybitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltenable-gpiossound-name-prefixcolorfunction-enumeratorcooling-levelsfan-supplypwmsmax-brightnesssimple-audio-card,namesimple-audio-card,aux-devssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,hp-det-gpiosimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersimple-audio-card,widgetssimple-audio-card,routingsound-daisystem-clock-frequencyenable-active-highstartup-delay-us