58D(  "tsd,rk3588-jaguarrockchip,rk3588 +$7Theobroma Systems RK3588-SBC Jaguaraliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/ethernet@fe1b0000/mmc@fe2e0000/mmc@fe2c0000/i2c@fd880000/rtc@6fcpus+cpu-mapcluster0core0 core1 core2 core3 cluster1core0 core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci,? F V0,k {@@  cpu@100cpuarm,cortex-a55psci,? k {@@ cpu@200cpuarm,cortex-a55psci,? k {@@ cpu@300cpuarm,cortex-a55psci,? k {@@ cpu@400cpuarm,cortex-a76psci,? F V0,k {@@ cpu@500cpuarm,cortex-a76psci,? k {@@ cpu@600cpuarm,cortex-a76psci,? F V0,k {@@ cpu@700cpuarm,cortex-a76psci,? k {@@  idle-states pscicpu-sleeparm,idle-state->Udfxv l2-cache-l0cache}@ l2-cache-l1cache}@l2-cache-l2cache}@l2-cache-l3cache}@l2-cache-b0cache}@l2-cache-b1cache}@l2-cache-b2cache}@l2-cache-b3cache}@l3-cachecache}0@firmwareopteelinaro,optee-tz%smcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0%smcclock-0 fixed-clock)׫splldisplay-subsystemrockchip,display-subsystemtimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmemusb@fc800000"rockchip,rk3588-ehcigeneric-ehci?usb&4okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci?usb&4okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci? !usb&4okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci? !usb&4okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(?jihkr&;ref_clksuspend_clkbus_clkutmipipeGhost" usb3-phy Outmi_wideX4_w 4disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXfsyscon@fd58c000rockchip,rk3588-sys-grfsysconX(syscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ )syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ*syscon@fd5b0000rockchip,rk3588-php-grfsyscon[$syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@8000rockchip,rk3588-usb2phyXophyapb?;phyclk usb480m_phy24okayhost-port4okay #syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@c000rockchip,rk3588-usb2phyXp phyapb?;phyclk usb480m_phy34okay host-port4okay!syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|F]q@VA.2Fq)׫ׄe/ׄ eZ р $i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=?ts ;i2cpclk$%.default+4okayfan@18 ti,amc6821regulator@42rockchip,rk8602B< Yvdd_npu_s0h|dp~&regulator-state-memregulator@43 rockchip,rk8603rockchip,rk8602C<Yvdd_cpu_big1_s0h|dp&regulator-state-memrtc@6f isil,isl1208ovop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8?]\abcd[7;aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop'&()**+ 4disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~?]\ ;aclkiface7& 4disabled'serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK?;baudclkapb_pclkD,,Itxrx$-.defaultS]4okaypwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm? ;pwmpclk$..defaultj 4disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm? ;pwmpclk$/.defaultj 4disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ? ;pwmpclk$0.defaultj 4disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0? ;pwmpclk$1.defaultj 4disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd+power-controller!rockchip,rk3588-power-controlleru+4okaypower-domain@8u+power-domain@9  ?!#" 234u+power-domain@10 ?!#"5upower-domain@11 ?!#"6upower-domain@12 ?789:upower-domain@13 +upower-domain@14(?;upower-domain@15 ?<upower-domain@16? =>?+upower-domain@17 ? @ABupower-domain@21? CDEFGHIJ+upower-domain@23?CAKupower-domain@14 ?;upower-domain@15?<upower-domain@22?Lupower-domain@24?[Z]MN+upower-domain@258?ZOupower-domain@268?QPQupower-domain@270?RSTU+upower-domain@28 ?VWupower-domain@29(?XYupower-domain@30?z{Zupower-domain@31@?W[\]^upower-domain@33!?WZ[upower-domain@34"?WZ[upower-domain@37%?2_upower-domain@38&?45upower-domain@40(`ui2s@fddc0000rockchip,rk3588-i2s-tdm?;mclk_txmclk_rxhclkFDaItx&Xtx-m 4disabledi2s@fddf0000rockchip,rk3588-i2s-tdm?445;mclk_txmclk_rxhclkF1DaItx&Xtx-m 4disabledi2s@fddfc000rockchip,rk3588-i2s-tdm?00,;mclk_txmclk_rxhclkF-DaIrx&Xrx-m 4disabledqos@fdf35000rockchip,rk3588-qossysconP 7qos@fdf35200rockchip,rk3588-qossysconR 8qos@fdf35400rockchip,rk3588-qossysconT 9qos@fdf35600rockchip,rk3588-qossysconV :qos@fdf36000rockchip,rk3588-qossyscon` Zqos@fdf39000rockchip,rk3588-qossyscon _qos@fdf3d800rockchip,rk3588-qossyscon `qos@fdf3e000rockchip,rk3588-qossyscon \qos@fdf3e200rockchip,rk3588-qossyscon [qos@fdf3e400rockchip,rk3588-qossyscon ]qos@fdf3e600rockchip,rk3588-qossyscon ^qos@fdf40000rockchip,rk3588-qossyscon Xqos@fdf40200rockchip,rk3588-qossyscon Yqos@fdf40400rockchip,rk3588-qossyscon Rqos@fdf40500rockchip,rk3588-qossyscon Sqos@fdf40600rockchip,rk3588-qossyscon Tqos@fdf40800rockchip,rk3588-qossyscon Uqos@fdf41000rockchip,rk3588-qossyscon Vqos@fdf41100rockchip,rk3588-qossyscon Wqos@fdf60000rockchip,rk3588-qossyscon =qos@fdf60200rockchip,rk3588-qossyscon >qos@fdf60400rockchip,rk3588-qossyscon ?qos@fdf61000rockchip,rk3588-qossyscon @qos@fdf61200rockchip,rk3588-qossyscon Aqos@fdf61400rockchip,rk3588-qossyscon Bqos@fdf62000rockchip,rk3588-qossyscon ;qos@fdf63000rockchip,rk3588-qossyscon0 <qos@fdf64000rockchip,rk3588-qossyscon@ Kqos@fdf66000rockchip,rk3588-qossyscon` Cqos@fdf66200rockchip,rk3588-qossysconb Dqos@fdf66400rockchip,rk3588-qossyscond Eqos@fdf66600rockchip,rk3588-qossysconf Fqos@fdf66800rockchip,rk3588-qossysconh Gqos@fdf66a00rockchip,rk3588-qossysconj Hqos@fdf66c00rockchip,rk3588-qossysconl Iqos@fdf66e00rockchip,rk3588-qossysconn Jqos@fdf67000rockchip,rk3588-qossysconp Lqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 5qos@fdf71000rockchip,rk3588-qossyscon 6qos@fdf72000rockchip,rk3588-qossyscon 2qos@fdf72200rockchip,rk3588-qossyscon" 3qos@fdf72400rockchip,rk3588-qossyscon$ 4qos@fdf80000rockchip,rk3588-qossyscon Oqos@fdf81000rockchip,rk3588-qossyscon Pqos@fdf81200rockchip,rk3588-qossyscon Qqos@fdf82000rockchip,rk3588-qossyscon Mqos@fdf82200rockchip,rk3588-qossyscon" Npcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0?CH>MR);aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`bbbb0c0" pcie-phy&"T @ @0 @@dbiapbconfigX). pwrpipe+ 4disabledlegacy-interrupt-controller& bpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0?DI?NSs);aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`dddd@c@e pcie-phy&"T @ @0 A@dbiapbconfigX*/ pwrpipe+ 4disabledlegacy-interrupt-controller& ddfi@fe060000rockchip,rk3588-dfi@&0:*fethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(?67Y^50;stmmacethclk_mac_refpclk_macaclk_macptp_ref&!X$ stmmaceth(;$Lg\mhi 4disabledmdiosnps,dwmac-mdio+stmmac-axi-configgrx-queues-confighqueue0queue1tx-queues-configiqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(?b_eTo;satapmaliverxoobrefasic+ 4disabledsata-port@0@e sata-phy  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(?dagVq;satapmaliverxoobrefasic+ 4disabledsata-port@0@" sata-phy  spi@fe2b0000 rockchip,sfc+@?/0;clk_sfchclk_sfc+ 4disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ ?  ;biuciuciu-driveciu-sample/:р.default $jkl&(4okayHR\mxmnmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ ?;biuciuciu-driveciu-sample/: .default$o&% 4disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.F-., V n6 (?,*+-.;corebusaxiblocktimer: $pqrs.default(Xcorebusaxiblocktimer4okayR*t5=CQmui2s@fe470000rockchip,rk3588-i2s-tdmG?+/(;mclk_txmclk_rxhclkF)-D,,Itxrx&&X*+ tx-mrx-m^.default($vwxyz{|}~ 4disabledi2s@fe480000rockchip,rk3588-i2s-tdmH?y}u;mclk_txmclk_rxhclkD,,ItxrxX^_ tx-mrx-m^.default($ 4disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI?;i2s_clki2s_hclkFDItxrx&&.default$ 4disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ?%;i2s_clki2s_hclkF"DItxrx&&.default$ 4disabledinterrupt-controller@fe600000 arm,gic-v3 `h &ya8+msi-controller@fe640000arm,gic-v3-itsdcmsi-controller@fe660000arm,gic-v3-itsfppi-partitionsinterrupt-partition-0interrupt-partition-1 dma-controller@fea10000arm,pl330arm,primecell@ VW?n ;apb_pclk,dma-controller@fea30000arm,pl330arm,primecell@ XY?o ;apb_pclki2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c?{ ;i2cpclk>$.default+ 4disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c?| ;i2cpclk?$.default+ 4disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c?} ;i2cpclk@$.default+ 4disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c?~ ;i2cpclkA$.default+ 4disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c? ;i2cpclkB$.default+ 4disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !?TW ;pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt?dc ;tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF?;spiclkapb_pclkD,,Itxrx $.default+ 4disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG?;spiclkapb_pclkD,,Itxrx $.default+ 4disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH?;spiclkapb_pclkDItxrx$.default+4okayFV pmic@0rockchip,rk806 .default$B@  & ,& 8& D& P& \& h& t& & &  &   &dvs1-null-pins gpio_pwrctrl2 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1|dp~0 Yvdd_gpu_s0 regulator-state-memdcdc-reg2Yvdd_cpu_lit_s0h|dp~0 regulator-state-memdcdc-reg3 Yvdd_log_s0h| L q0regulator-state-mem  qdcdc-reg4 Yvdd_vdenc_s0h|dp~0regulator-state-memdcdc-reg5 Yvdd_ddr_s0h| L 0regulator-state-mem  Pdcdc-reg6 Yvdd2_ddr_s3h|regulator-state-mem dcdc-reg7Yvdd_2v0_pldo_s3h|0regulator-state-mem  dcdc-reg8 Yvcc_3v3_s3h|2Z2Zmregulator-state-mem  2Zdcdc-reg9 Yvddq_ddr_s0h|regulator-state-memdcdc-reg10 Yvcc_1v8_s3h|w@w@uregulator-state-mem  w@pldo-reg1 Yvcca_1v8_s0h|w@w@regulator-state-mempldo-reg2 Yvcc_1v8_s0h|w@w@regulator-state-mem w@pldo-reg3 Yvdda_1v2_s0h|OOregulator-state-mempldo-reg4 Yvcca_3v3_s0h|2Z2Z0regulator-state-mempldo-reg5 Yvccio_sd_s0h|w@2Z0nregulator-state-mempldo-reg6 Ypldo6_s3h|w@w@regulator-state-mem  w@nldo-reg1 Yvdd_0v75_s3h| q qregulator-state-mem   qnldo-reg2Yvdda_ddr_pll_s0h| P Pregulator-state-mem  Pnldo-reg3 Yvdda_0v75_s0h| q qregulator-state-memnldo-reg4 Yvdda_0v85_s0h| P Pregulator-state-memnldo-reg5 Yvdd_0v75_s0h| q qregulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI?;spiclkapb_pclkDItxrx $.default+ 4disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL?;baudclkapb_pclkD,, Itxrx$.default]S 4disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM?;baudclkapb_pclkD, , Itxrx$.default]S4okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN?;baudclkapb_pclkD, , Itxrx$.default]S4okay 7serial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO?;baudclkapb_pclkD Itxrx$.default]S 4disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP?;baudclkapb_pclkD Itxrx$.default]S 4disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ?;baudclkapb_pclkD Itxrx$.default]S 4disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR?;baudclkapb_pclkDaaItxrx$.default]S4okayserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS?;baudclkapb_pclkDa a Itxrx$.default]S 4disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT?;baudclkapb_pclkDa a Itxrx$.default]S 4disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?LK ;pwmpclk$.defaultj 4disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?LK ;pwmpclk$.defaultj 4disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?LK ;pwmpclk$.defaultj 4disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?LK ;pwmpclk$.defaultj 4disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?ON ;pwmpclk$.defaultj 4disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?ON ;pwmpclk$.defaultj 4disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?ON ;pwmpclk$.defaultj 4disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?ON ;pwmpclk$.defaultj 4disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?RQ ;pwmpclk$.defaultj 4disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?RQ ;pwmpclk$.defaultj 4disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?RQ ;pwmpclk$.defaultj 4disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?RQ ;pwmpclk$.defaultj 4disabledtsadc@fec00000rockchip,rk3588-tsadc?;tsadcapb_pclkFVXVWtsadc-apbtsadc X o $  .gpiootpout 4okayadc@fec10000rockchip,rk3588-saradc ?;saradcapb_pclkXU saradc-apb4okay i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c? ;i2cpclkC$.default+ 4disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c? ;i2cpclkD$.default+4okayeeprom@54st,24c04atmel,24c04T  mi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c? ;i2cpclkE$.default+4okayregulator@42rockchip,rk8602B<Yvdd_cpu_big0_s0h|dp&regulator-state-memspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ?;spiclkapb_pclkDa aItxrx $.default+ 4disabledefuse@fecc0000rockchip,rk3588-otp ?;otpapb_pclkphyarbX otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[?p ;apb_pclkaphy@fee00000rockchip,rk3588-naneng-combphy?vW ;refapbpipeFVX<Cphyapb $  4disabledephy@fee20000rockchip,rk3588-naneng-combphy?xW ;refapbpipeFVX>Ephyapb $  4disabled"sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl+gpio@fd8a0000rockchip,gpio-bank?qr &gpio@fec20000rockchip,gpio-bank?st &mdot2e-w-disable1-n-hog ,  2 =m.2 E-key W_DISABLE1# Ggpio@fec30000rockchip,gpio-bank?uv @ &gpio@fec40000rockchip,gpio-bank?wx ` &gpio@fec50000rockchip,gpio-bank?yz &mdot2e-w-disable2-n-hog , 2 =m.2 E-key W_DISABLE2# Gpcfg-pull-up Ppcfg-pull-down ]pcfg-pull-none lpcfg-pull-none-drv-level-2 l ypcfg-pull-up-drv-level-1 P ypcfg-pull-up-drv-level-2 P ypcfg-pull-none-smt l auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-bus8 pemmc-clk remmc-cmd qemmc-data-strobe semmc-reset eth1fspigmac1gpuhdmii2c0i2c0m2-xfer %i2c1i2c1m4-xfer   i2c2i2c2m0-xfer   i2c3i2c3m0-xfer   i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2c6i2c6m4-xfer   i2c7i2c7m0-xfer   i2c8i2c8m2-xfer   i2s0i2s0-lrck vi2s0-sclk wi2s0-sdi0 xi2s0-sdi1 yi2s0-sdi2 zi2s0-sdi3 {i2s0-sdo0 |i2s0-sdo1 }i2s0-sdo2 ~i2s0-sdo3 i2s1i2s1m0-lrck i2s1m0-sclk i2s1m0-sdi0 i2s1m0-sdi1 i2s1m0-sdi2 i2s1m0-sdi3 i2s1m0-sdo0  i2s1m0-sdo1  i2s1m0-sdo2  i2s1m0-sdo3  i2s2i2s2m1-lrck i2s2m1-sclk  i2s2m1-sdi  i2s2m1-sdo  i2s3i2s3-lrck i2s3-sclk i2s3-sdi i2s3-sdo jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp pmupwm0pwm0m0-pins .pwm1pwm1m0-pins /pwm2pwm2m0-pins 0pwm3pwm3m0-pins 1pwm4pwm4m0-pins  pwm5pwm5m0-pins pwm6pwm6m0-pins  pwm7pwm7m0-pins  pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins  pwm12pwm12m0-pins  pwm13pwm13m0-pins  pwm14pwm14m0-pins  pwm15pwm15m0-pins  refclksatasata0sata1sata2sdiosdiom1-pins` osdmmcsdmmc-bus4@ jsdmmc-clk lsdmmc-cmd kspdif0spdif1spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m1-pins0 spi1m1-cs0 spi1m1-cs1 spi2spi2m2-pins0  spi2m2-cs0 spi3spi3m1-pins0  spi3m1-cs0 spi3m1-cs1 spi4spi4m0-pins0 spi4m0-cs0 spi4m0-cs1 tsadctsadc-shut uart0uart0m0-xfer -uart1uart1m1-xfer   uart2uart2m0-xfer  uart3uart3m2-xfer   uart3-rtsn  uart4uart4m1-xfer   uart5uart5m1-xfer   uart6uart6m1-xfer   uart7uart7m0-xfer   uart8uart8m1-xfer   uart9uart9m1-xfer   vopbt656gpio-functsadc-gpio-func eth0eth0-pins gmac0gmac0-miim gmac0-rx-bus20 gmac0-tx-bus20 gmac0-rgmii-clk  gmac0-rgmii-bus@   etherneteth-reset ledsled1-pin video-codec@fdc70000rockchip,rk3588-av1-vpulvdpuFACVׄׄ?AC ;aclkhclk& Xsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\i2s@fddc8000rockchip,rk3588-i2s-tdm܀?;mclk_txmclk_rxhclkFDaItx&Xtx-m 4disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@?99?;mclk_txmclk_rxhclkF6DaItx&Xtx-m 4disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀?++';mclk_txmclk_rxhclkF(DaIrx&Xrx-m 4disabledi2s@fde00000rockchip,rk3588-i2s-tdm?&&";mclk_txmclk_rxhclkF#DaIrx&Xrx-m 4disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0?@E;JOt);aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` pcie-phy&"T @ @0 @@dbiapbconfigX&+ pwrpipe 4disabledlegacy-interrupt-controller& pcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0?AF<KPu);aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` pcie-phy&"T @ @@0 @@@dbiapbconfigX', pwrpipe 4disabledlegacy-interrupt-controller& pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0?BG=LQ);aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` c  pcie-phy&"T @ @0 @@dbiapbconfigX(- pwrpipe+4okay  legacy-interrupt-controller& ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(?67X]40;stmmacethclk_mac_refpclk_macaclk_macptp_ref&!X# stmmaceth(;$L\m4okay output  rgmii .default$     'mdiosnps,dwmac-mdio+ethernet-phy@6ethernet-phy-ieee802.3-c22?stmmac-axi-configrx-queues-configqueue0queue1tx-queues-configqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(?c`fUp;satapmaliverxoobrefasic+ 4disabledsata-port@0@ sata-phy  phy@fee10000rockchip,rk3588-naneng-combphy?wW ;refapbpipeFVX=Dphyapb $ 4okayphy@fee80000rockchip,rk3588-pcie3-phy?y;pclkXHphy $ 5 4disabledadc-keys adc-keys F Rbuttons cw@ }dbutton-bios-disable BIOS_DISABLE h chosen serial2:115200n8dc-12v-regulatorregulator-fixedYdc_12vh|emmc-pwrseqmmc-pwrseq-emmc$.default tleds gpio-leds.default$led-1 , heartbeat heartbeat pps pps-gpio ,vcc-1v1-nldo-s3-regulatorregulator-fixedYvcc_1v1_nldo_s3h|&vcc-1v2-s3-regulatorregulator-fixed Yvcc_1v2_s3h|OO&vcc-2v8-s3-regulatorregulator-fixed Yvcc_2v8_s3h|**mvcc-5v0-usb-a-regulatorregulator-fixed Yusb_a_vccLK@LK@&   #vcc-5v0-usb-c1-regulatorregulator-fixed Y5v_usbc1LK@LK@   vcc-5v0-usb-c2-regulatorregulator-fixed Y5v_usbc2LK@LK@  vcc3v3-mdot2-regulatorregulator-fixed Yvcc3v3_mdot2h|2Z2Zvcc5v0-sys-regulatorregulator-fixed Yvcc5v0_sysh|LK@LK@&vcc5v0-usb-regulatorregulator-fixed Yvcc5v0_usbh|LK@LK@& compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0mmc1rtc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesportsinterrupt-namesrangesphysphy-namespower-domainsstatusclock-namesdr_modephy_typeresetssnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirkreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmu#iommu-cellsdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybroken-cdbus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-ddr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobemmc-pwrseqno-sdiono-sdnon-removablesupports-cqerockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csgpio-controller#gpio-cellsspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendlinux,rs485-enabled-at-boot-timerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplypagesizevcc-supplybitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesgpiosoutput-lowline-namegpio-hogbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsreset-gpiosvpcie3v3-supplyclock_in_outphy-handlephy-modetx_delayrx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrockchip,phy-grfio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltstdout-pathlinux,default-triggercolorenable-active-high