8,( Uedgeble,neural-compute-module-6a-ioedgeble,neural-compute-module-6brockchip,rk3588 +7Edgeble Neu6B IO Boardaliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55 psci+ 2 B0,W gt@@  cpu@100cpuarm,cortex-a55 psci+ W gt@@ cpu@200cpuarm,cortex-a55 psci+ W gt@@ cpu@300cpuarm,cortex-a55 psci+ W gt@@ cpu@400cpuarm,cortex-a76 psci+ 2 B0,W gt@@cpu@500cpuarm,cortex-a76 psci+ W gt@@cpu@600cpuarm,cortex-a76 psci+ 2 B0,W gt@@cpu@700cpuarm,cortex-a76 psci+ W gt@@ idle-states pscicpu-sleeparm,idle-state*AdRxb l2-cache-l0cacheiv@s l2-cache-l1cacheiv@sl2-cache-l2cacheiv@sl2-cache-l3cacheiv@sl2-cache-b0cacheiv@sl2-cache-b1cacheiv@sl2-cache-b2cacheiv@sl2-cache-b3cacheiv@sl3-cachecachei0v@sfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splldisplay-subsystemrockchip,display-subsystemtimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmemusb@fc800000"rockchip,rk3588-ehcigeneric-ehci+usb  disabledusb@fc840000"rockchip,rk3588-ohcigeneric-ohci+usb  disabledusb@fc880000"rockchip,rk3588-ehcigeneric-ehci+usb  disabledusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci+usb  disabledusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(+jihkr&'ref_clksuspend_clkbus_clkutmipipe3host  usb3-phy ;utmi_wideD4Kc  disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXbsyscon@fd58c000rockchip,rk3588-sys-grfsysconX$syscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ %syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ&syscon@fd5b0000rockchip,rk3588-php-grfsyscon[!syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@8000rockchip,rk3588-usb2phyDophyapb+'phyclk usb480m_phy2  disabledhost-port  disabledsyscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@c000rockchip,rk3588-usb2phyDp phyapb+'phyclk usb480m_phy3  disabledhost-port  disabledsyscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|2]q@BA.2Fq)׫ׄe/ׄ eZ р !i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=+ts 'i2cpclk"default+  disabledvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8+]\abcd[7'aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop'#$.%?&P'  disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~+]\ 'aclkiface]  disabled#serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK+'baudclkapb_pclkj((otxrx)defaulty  disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ 'pwmpclk*default  disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ 'pwmpclk+default  disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm + 'pwmpclk,default okaypwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ 'pwmpclk-default  disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd'power-controller!rockchip,rk3588-power-controller+ okaypower-domain@8+power-domain@9  +!#" ./0+power-domain@10 +!#"1power-domain@11 +!#"2power-domain@12 +3456power-domain@13 +power-domain@14(+7power-domain@15 +8power-domain@16+ 9:;+power-domain@17 + <=>power-domain@21+ ?@ABCDEF+power-domain@23+CAGpower-domain@14 +7power-domain@15+8power-domain@22+Hpower-domain@24+[Z]IJ+power-domain@258+ZKpower-domain@268+QLMpower-domain@270+NOPQ+power-domain@28 +RSpower-domain@29(+TUpower-domain@30+z{Vpower-domain@31@+WWXYZpower-domain@33!+WZ[power-domain@34"+WZ[power-domain@37%+2[power-domain@38&+45power-domain@40(\i2s@fddc0000rockchip,rk3588-i2s-tdm+'mclk_txmclk_rxhclk2j]otxDtx-m  disabledi2s@fddf0000rockchip,rk3588-i2s-tdm+445'mclk_txmclk_rxhclk21j]otxDtx-m  disabledi2s@fddfc000rockchip,rk3588-i2s-tdm+00,'mclk_txmclk_rxhclk2-j]orxDrx-m  disabledqos@fdf35000rockchip,rk3588-qossysconP 3qos@fdf35200rockchip,rk3588-qossysconR 4qos@fdf35400rockchip,rk3588-qossysconT 5qos@fdf35600rockchip,rk3588-qossysconV 6qos@fdf36000rockchip,rk3588-qossyscon` Vqos@fdf39000rockchip,rk3588-qossyscon [qos@fdf3d800rockchip,rk3588-qossyscon \qos@fdf3e000rockchip,rk3588-qossyscon Xqos@fdf3e200rockchip,rk3588-qossyscon Wqos@fdf3e400rockchip,rk3588-qossyscon Yqos@fdf3e600rockchip,rk3588-qossyscon Zqos@fdf40000rockchip,rk3588-qossyscon Tqos@fdf40200rockchip,rk3588-qossyscon Uqos@fdf40400rockchip,rk3588-qossyscon Nqos@fdf40500rockchip,rk3588-qossyscon Oqos@fdf40600rockchip,rk3588-qossyscon Pqos@fdf40800rockchip,rk3588-qossyscon Qqos@fdf41000rockchip,rk3588-qossyscon Rqos@fdf41100rockchip,rk3588-qossyscon Sqos@fdf60000rockchip,rk3588-qossyscon 9qos@fdf60200rockchip,rk3588-qossyscon :qos@fdf60400rockchip,rk3588-qossyscon ;qos@fdf61000rockchip,rk3588-qossyscon <qos@fdf61200rockchip,rk3588-qossyscon =qos@fdf61400rockchip,rk3588-qossyscon >qos@fdf62000rockchip,rk3588-qossyscon 7qos@fdf63000rockchip,rk3588-qossyscon0 8qos@fdf64000rockchip,rk3588-qossyscon@ Gqos@fdf66000rockchip,rk3588-qossyscon` ?qos@fdf66200rockchip,rk3588-qossysconb @qos@fdf66400rockchip,rk3588-qossyscond Aqos@fdf66600rockchip,rk3588-qossysconf Bqos@fdf66800rockchip,rk3588-qossysconh Cqos@fdf66a00rockchip,rk3588-qossysconj Dqos@fdf66c00rockchip,rk3588-qossysconl Eqos@fdf66e00rockchip,rk3588-qossysconn Fqos@fdf67000rockchip,rk3588-qossysconp Hqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 1qos@fdf71000rockchip,rk3588-qossyscon 2qos@fdf72000rockchip,rk3588-qossyscon .qos@fdf72200rockchip,rk3588-qossyscon" /qos@fdf72400rockchip,rk3588-qossyscon$ 0qos@fdf80000rockchip,rk3588-qossyscon Kqos@fdf81000rockchip,rk3588-qossyscon Lqos@fdf81200rockchip,rk3588-qossyscon Mqos@fdf82000rockchip,rk3588-qossyscon Iqos@fdf82200rockchip,rk3588-qossyscon" Jpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0+CH>MR)'aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` ^^^^+:0_0B  pcie-phy"T @ @0 @@dbiapbconfigD). pwrpipe+  disabledlegacy-interrupt-controllerL ^pcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0+DI?NSs)'aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` ````+:@_@Ba pcie-phy"T @ @0 A@dbiapbconfigD*/ pwrpipe+  disabledlegacy-interrupt-controllerL `dfi@fe060000rockchip,rk3588-dfi@&0:Pbethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(+67Y^50'stmmacethclk_mac_refpclk_macaclk_macptp_ref!D$ stmmaceth$a!rcde  disabledmdiosnps,dwmac-mdio+stmmac-axi-configcrx-queues-configdqueue0queue1tx-queues-configequeue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(+b_eTo'satapmaliverxoobrefasic+ okaysata-port@0*@a sata-phy7 F sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(+dagVq'satapmaliverxoobrefasic+  disabledsata-port@0*@  sata-phy7 F spi@fe2b0000 rockchip,sfc+@+/0'clk_sfchclk_sfc+  disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ +  'biuciuciu-driveciu-sampleU` defaultfghi( okaynxjkmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ +'biuciuciu-driveciu-sampleU` defaultl%  disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.2-., B n6 (+,*+-.'corebusaxiblocktimer` mnopqdefault(Dcorebusaxiblocktimer okayni2s@fe470000rockchip,rk3588-i2s-tdmG++/('mclk_txmclk_rxhclk2)-j((otxrx&D*+ tx-mrx-mdefault(rstuvwxyz{  disabledi2s@fe480000rockchip,rk3588-i2s-tdmH+y}u'mclk_txmclk_rxhclkj((otxrxD^_ tx-mrx-mdefault(|}~  disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI+'i2s_clki2s_hclk2jotxrx&default  disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ+%'i2s_clki2s_hclk2"jotxrx&default  disabledinterrupt-controller@fe600000 arm,gic-v3 `h L4a>8I+msi-controller@fe640000arm,gic-v3-itsdIX_msi-controller@fe660000arm,gic-v3-itsfIXppi-partitionsinterrupt-partition-0cinterrupt-partition-1c dma-controller@fea10000arm,pl330arm,primecell@ VWl+n 'apb_pclk(dma-controller@fea30000arm,pl330arm,primecell@ XYl+o 'apb_pclki2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c+{ 'i2cpclk>default+  disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c+| 'i2cpclk?default+  disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c+} 'i2cpclk@default+  disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c+~ 'i2cpclkAdefault+  disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ 'i2cpclkBdefault+  disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !+TW 'pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt+dc 'tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF+'spiclkapb_pclkj((otxrx default+  disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG+'spiclkapb_pclkj((otxrx default+  disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH+'spiclkapb_pclkjotxrxdefault+ okay2B pmic@0rockchip,rk806B@ default -:GT`pdvs1-null-pins|gpio_pwrctrl2 pin_fun0dvs2-null-pins|gpio_pwrctrl2 pin_fun0dvs3-null-pins|gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1 vdd_gpu_s0dp~0regulator-state-mem dcdc-reg2vdd_cpu_lit_s0 %dp~0 regulator-state-mem dcdc-reg3 vdd_log_s0 % L q0regulator-state-mem  9 qdcdc-reg4 vdd_vdenc_s0 %dp~ U q0regulator-state-mem dcdc-reg5 vdd_ddr_s0 % L 0regulator-state-mem  9 Pdcdc-reg6 vdd2_ddr_s3 %regulator-state-mem ndcdc-reg7vdd_2v0_pldo_s3 %0regulator-state-mem n 9dcdc-reg8 vcc_3v3_s3 %2Z2Zjregulator-state-mem n 92Zdcdc-reg9 vddq_ddr_s0 %regulator-state-mem dcdc-reg10 vcc_1v8_s3 %w@w@regulator-state-mem n 9w@pldo-reg1 avcc_1v8_s0 %w@w@regulator-state-mem pldo-reg2 vcc_1v8_s0 %w@w@regulator-state-mem  9w@pldo-reg3 avdd_1v2_s0 %OOregulator-state-mem pldo-reg4 vcc_3v3_s0 %2Z2Z0regulator-state-mem pldo-reg5 vccio_sd_s0 %w@2Z0kregulator-state-mem pldo-reg6 pldo6_s3 %w@w@regulator-state-mem n 9w@nldo-reg1 vdd_0v75_s3 % q qregulator-state-mem n 9 qnldo-reg2vdd_ddr_pll_s0 % P Pregulator-state-mem  9 Pnldo-reg3 avdd_0v75_s0 % q qregulator-state-mem nldo-reg4 vdd_0v85_s0 % P Pregulator-state-mem nldo-reg5 vdd_0v75_s0 % q qregulator-state-mem spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI+'spiclkapb_pclkjotxrx default+  disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL+'baudclkapb_pclkj(( otxrxdefaulty  disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM+'baudclkapb_pclkj( ( otxrxdefaulty okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN+'baudclkapb_pclkj( ( otxrxdefaulty  disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO+'baudclkapb_pclkj otxrxdefaulty  disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP+'baudclkapb_pclkj otxrxdefaulty  disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ+'baudclkapb_pclkj otxrxdefaulty okayserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR+'baudclkapb_pclkj]]otxrxdefaulty okayserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS+'baudclkapb_pclkj] ] otxrxdefaulty  disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT+'baudclkapb_pclkj] ] otxrxdefaulty  disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK 'pwmpclkdefault  disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK 'pwmpclkdefault  disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +LK 'pwmpclkdefault  disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+LK 'pwmpclkdefault  disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON 'pwmpclkdefault  disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON 'pwmpclkdefault  disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +ON 'pwmpclkdefault  disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ON 'pwmpclkdefault  disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ 'pwmpclkdefault  disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ 'pwmpclkdefault  disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +RQ 'pwmpclkdefault  disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+RQ 'pwmpclkdefault  disabledtsadc@fec00000rockchip,rk3588-tsadc+'tsadcapb_pclk2BDVWtsadc-apbtsadc     gpiootpout   disabledadc@fec10000rockchip,rk3588-saradc +'saradcapb_pclkDU saradc-apb  disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c+ 'i2cpclkCdefault+ okayrtc@51haoyu,hym8563Q hym8563default i2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c+ 'i2cpclkDdefault+  disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ 'i2cpclkEdefault+  disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ+'spiclkapb_pclkj] ]otxrx default+  disabledefuse@fecc0000rockchip,rk3588-otp +'otpapb_pclkphyarbD otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[l+p 'apb_pclk]phy@fee00000rockchip,rk3588-naneng-combphy+vW 'refapbpipe2BD<Cphyapb ! & okayaphy@fee20000rockchip,rk3588-naneng-combphy+xW 'refapbpipe2BD>Ephyapb ! &  disabled sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl+gpio@fd8a0000rockchip,gpio-bank+qr` < Lpgpio@fec20000rockchip,gpio-bank+st` < Lpgpio@fec30000rockchip,gpio-bank+uv` <@ Lpgpio@fec40000rockchip,gpio-bank+wx` <` Lpgpio@fec50000rockchip,gpio-bank+yz` < Lppcfg-pull-up Hpcfg-pull-down Upcfg-pull-none dpcfg-pull-none-drv-level-2 d qpcfg-pull-up-drv-level-1 H qpcfg-pull-up-drv-level-2 H qpcfg-pull-none-smt d auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout memmc-bus8 nemmc-clk oemmc-cmd pemmc-data-strobe qeth1fspigmac1gpuhdmii2c0i2c0m0-xfer "i2c1i2c1m0-xfer  i2c2i2c2m0-xfer   i2c3i2c3m0-xfer   i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2c6i2c6m0-xfer   i2c7i2c7m0-xfer   i2c8i2c8m0-xfer   i2s0i2s0-lrck ri2s0-sclk si2s0-sdi0 ti2s0-sdi1 ui2s0-sdi2 vi2s0-sdi3 wi2s0-sdo0 xi2s0-sdo1 yi2s0-sdo2 zi2s0-sdo3 {i2s1i2s1m0-lrck |i2s1m0-sclk }i2s1m0-sdi0 ~i2s1m0-sdi1 i2s1m0-sdi2 i2s1m0-sdi3 i2s1m0-sdo0  i2s1m0-sdo1  i2s1m0-sdo2  i2s1m0-sdo3  i2s2i2s2m1-lrck i2s2m1-sclk  i2s2m1-sdi  i2s2m1-sdo  i2s3i2s3-lrck i2s3-sclk i2s3-sdi i2s3-sdo jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp pmupwm0pwm0m0-pins *pwm1pwm1m0-pins +pwm2pwm2m1-pins  ,pwm3pwm3m0-pins -pwm4pwm4m0-pins  pwm5pwm5m0-pins pwm6pwm6m0-pins  pwm7pwm7m0-pins  pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins  pwm12pwm12m0-pins  pwm13pwm13m0-pins  pwm14pwm14m0-pins  pwm15pwm15m0-pins  refclksatasata0sata1sata2sdiosdiom1-pins` lsdmmcsdmmc-bus4@ isdmmc-clk fsdmmc-cmd gsdmmc-det hspdif0spdif1spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m1-pins0 spi1m1-cs0 spi1m1-cs1 spi2spi2m2-pins0  spi2m2-cs0 spi3spi3m1-pins0  spi3m1-cs0 spi3m1-cs1 spi4spi4m0-pins0 spi4m0-cs0 spi4m0-cs1 tsadctsadc-shut uart0uart0m1-xfer  )uart1uart1m1-xfer   uart2uart2m0-xfer  uart3uart3m1-xfer   uart4uart4m1-xfer   uart5uart5m1-xfer   uart6uart6m0-xfer   uart7uart7m2-xfer   uart8uart8m1-xfer   uart9uart9m1-xfer   vopbt656gpio-functsadc-gpio-func eth0gmac0hym8563hym8563-int video-codec@fdc70000rockchip,rk3588-av1-vpulvdpu2ACBׄׄ+AC 'aclkhclk Dsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\i2s@fddc8000rockchip,rk3588-i2s-tdm܀+'mclk_txmclk_rxhclk2j]otxDtx-m  disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@+99?'mclk_txmclk_rxhclk26j]otxDtx-m  disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀+++''mclk_txmclk_rxhclk2(j]orxDrx-m  disabledi2s@fde00000rockchip,rk3588-i2s-tdm+&&"'mclk_txmclk_rxhclk2#j]orxDrx-m  disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+@E;JOt)'aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` +:B pcie-phy"T @ @0 @@dbiapbconfigD&+ pwrpipe  disabledlegacy-interrupt-controllerL pcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+AF<KPu)'aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` +:B pcie-phy"T @ @@0 @@@dbiapbconfigD', pwrpipe  disabledlegacy-interrupt-controllerL pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0+BG=LQ)'aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` +: _ B pcie-phy"T @ @0 @@dbiapbconfigD(- pwrpipe+  disabledlegacy-interrupt-controllerL ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(+67X]40'stmmacethclk_mac_refpclk_macaclk_macptp_ref!D# stmmaceth$a!r  disabledmdiosnps,dwmac-mdio+stmmac-axi-configrx-queues-configqueue0queue1tx-queues-configqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(+c`fUp'satapmaliverxoobrefasic+  disabledsata-port@0*@ sata-phy7 F phy@fee10000rockchip,rk3588-naneng-combphy+wW 'refapbpipe2BD=Dphyapb ! &  disabledphy@fee80000rockchip,rk3588-pcie3-phy+y'pclkDHphy !   disabledvcc12v-dcin-regulatorregulator-fixed vcc12v_dcin %vcc5v0-sys-regulatorregulator-fixed vcc5v0_sys %LK@LK@ vcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3 % chosen serial2:1500000n8 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesportsinterrupt-namesrangesphysphy-namespower-domainsstatusclock-namesdr_modephy_typeresetssnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirkreset-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmu#iommu-cellsdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-nameregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-off-in-suspendregulator-always-onregulator-suspend-microvoltregulator-init-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellswakeup-sourcebitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfvin-supplystdout-path