n8gt(g<)tronsmart,orion-r68-metarockchip,rk3368 +7Rockchip Orion R68aliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/ethernet@ff290000/mmc@ff0c0000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53psciarm-pmuarm,armv8-pmuv3`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockn6%xin24m8Fmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @E S  D r vZbiuciuciu-driveciu-samplef q xresetokaydefault mmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @Eр S  E s wZbiuciuciu-driveciu-samplef !q xreset disabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@Eр S  G u yZbiuciuciu-driveciu-samplef #q xresetokay$default saradc@ff100000rockchip,saradc $2S I [Zsaradcapb_pclkq W xsaradc-apbokayDspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spiS A RZspiclkapb_pclk ,default+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spiS B SZspiclkapb_pclk -default+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spiS C TZspiclkapb_pclk )default !+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+Zi2cS Ndefault" disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+Zi2cS Odefault# disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+Zi2cS Pdefault$ disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+Zi2cS Qdefault% disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartn6S M UZbaudclkapb_pclk 7PZ disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartn6S N VZbaudclkapb_pclk 8PZ disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartn6S P XZbaudclkapb_pclk :PZ disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartn6S Q YZbaudclkapb_pclk ;PZokaydefault&dma-controller@ff250000arm,pl330arm,primecell%@grS  Zapb_pclkthermal-zonescpu-thermald'tripscpu_alert0$passive(cpu_alert18passive)cpu_crits criticalcooling-mapsmap0(0map1)0 gpu-thermald'tripsgpu_alert08passive*gpu_crit8 criticalcooling-mapsmap0*0tsadc@ff280000rockchip,rk3368-tsadc( %S H ZZtsadcapb_pclkq  xtsadc-apbinitdefaultsleep+, +-s disabled'ethernet@ff290000rockchip,rk3368-gmac) DmacirqT-8S  f g c ]MZstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macokaya q.input/rgmiidefault0 1  'B@0usb@ff500000 generic-ehciP S okayusb@ff5800002rockchip,rk3368-usbrockchip,rk3066-usbsnps,dwc2X S Zotgotg@@ okaydma-controller@ff600000arm,pl330arm,primecell`@grS  Zapb_pclkGi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2ceS LZi2c <default2+okaysyr827@40silergy,syr827@.Kvdd_cpuZ,v 4`@3rtc@51haoyu,hym8563Q8%xin32ki2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+Zi2cS Mdefault4 disabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault5S _ disabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault6S _ disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh S _ disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default7S _ disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uartiS O WZbaudclkapb_pclk 9default8PZokaymbox@ff6b0000rockchip,rk3368-mailboxk0S E Zpclk_mailbox disabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdspower-controller!rockchip,rk3368-power-controller+Jpower-domain@12 S       c h g n o r s f d d h i l k j n m$9:;<=>?@Apower-domain@14 S  o p BCDpower-domain@16S @Esyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdsKio-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-mode%RB1RB?RB ORBclock-controller@ff760000rockchip,rk3368-cruvSFZxin24mT-8[ syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw-io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdtS p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  BS a U Zpclktimerspdif@ff880000rockchip,rk3368-spdif 6S S  ZmclkhclkhGmtxdefaultH disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (Zi2s_clki2s_hclkS T hGGmtxrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5Zi2s_clki2s_hclkS R hGGmtxrxdefaultI disablediommu@ff900800rockchip,iommu S  ZaclkifacewJ  disablediommu@ff914000rockchip,iommu @P S  ZaclkifacewJ  disablediommu@ff930300rockchip,iommu S  ZaclkifacewJ  disablediommu@ff9a0440rockchip,iommu @@@ S  Zaclkiface disablediommu@ff9a0800rockchip,iommu  S  Zaclkiface disabledqos@ffad0000rockchip,rk3368-qossyscon 9qos@ffad0080rockchip,rk3368-qossyscon :qos@ffad0100rockchip,rk3368-qossyscon ;qos@ffad0180rockchip,rk3368-qossyscon <qos@ffad0200rockchip,rk3368-qossyscon =qos@ffad0280rockchip,rk3368-qossyscon >qos@ffad0300rockchip,rk3368-qossyscon ?qos@ffad0380rockchip,rk3368-qossyscon @qos@ffad0400rockchip,rk3368-qossyscon Aqos@ffae0000rockchip,rk3368-qossyscon Bqos@ffae0100rockchip,rk3368-qossyscon Cqos@ffae0180rockchip,rk3368-qossyscon Dqos@ffaf0000rockchip,rk3368-qossyscon Eefuse@ffb00000rockchip,rk3368-efuse +S q Zpclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400@ @ `   pinctrlrockchip,rk3368-pinctrlT-K+gpio@ff750000rockchip,gpio-bankuS @ QUgpio@ff780000rockchip,gpio-bankxS A Rgpio@ff790000rockchip,gpio-bankyS B SSgpio@ff7a0000rockchip,gpio-bankzS C T1pcfg-pull-upNpcfg-pull-downQpcfg-pull-noneOpcfg-pull-none-12ma, Pemmcemmc-clk;Lemmc-cmd;Memmc-pwr;Nemmc-bus1;Nemmc-bus4@;NNNNemmc-bus8;MMMMMMMMemmc-reset;ORgmacrgmii-pins;OOOP P PPP POOOOOO0rmii-pins;OOOP P POOOOi2c0i2c0-xfer ;OO2i2c1i2c1-xfer ;OO4i2c2i2c2-xfer ; OO"i2c3i2c3-xfer ;OO#i2c4i2c4-xfer ;OO$i2c5i2c5-xfer ;OO%i2si2s-8ch-bus; O OOOOOOOOIpwm0pwm0-pin;O5pwm1pwm1-pin;O6pwm3pwm3-pin;O7sdio0sdio0-bus1;Nsdio0-bus4@;NNNNsdio0-cmd;Nsdio0-clk;Osdio0-cd;Nsdio0-wp;Nsdio0-pwr;Nsdio0-bkpwr;Nsdio0-int;Nsdmmcsdmmc-clk; L sdmmc-cmd; M sdmmc-cd; M sdmmc-bus1;Msdmmc-bus4@;MMMMspdifspdif-tx;OHspi0spi0-clk;Nspi0-cs0;Nspi0-cs1;Nspi0-tx;Nspi0-rx;Nspi1spi1-clk;Nspi1-cs0;Nspi1-cs1;Nspi1-rx;Nspi1-tx;Nspi2spi2-clk; Nspi2-cs0; N!spi2-rx; N spi2-tx; Ntsadcotp-pin;O+otp-out;O,uart0uart0-xfer ;NOuart0-cts;Ouart0-rts;Ouart1uart1-xfer ;NOuart1-cts;Ouart1-rts;Ouart2uart2-xfer ;NO8uart3uart3-xfer ;NOuart3-cts;Ouart3-rts;Ouart4uart4-xfer ;NO&uart4-cts;Ouart4-rts;Opcfg-pull-none-drv-8ma,Lpcfg-pull-up-drv-8ma,Mkeyspwr-key;QTledsstby-pwren; OWled-ctl;OVusbhost-vbus-drv;OXchosenIserial2:115200n8memorymemoryemmc-pwrseqmmc-pwrseq-emmcRdefault USexternal-gmac-clock fixed-clock8sY@ %ext_gmac.gpio-keys gpio-keysdefaultTkey-powera [U oGPIO Powerutgpio-leds gpio-ledsled-0 [1oorion:red:leddefaultVonled-1 [U oorion:blue:leddefaultWoffvcc18-regulatorregulator-fixedKvcc_18vw@w@3vcc-host-regulatorregulator-fixed UdefaultX Kvcc_host3vcc-io-regulatorregulator-fixedKvcc_iov2Z2Z3Yvcc-lan-regulatorregulator-fixedKvcc_lanv2Z2ZY/vcc-sd-regulatorregulator-fixedKvcc_sd 1 vw@2ZYvcc-sys-regulatorregulator-fixedKvcc_sysvLK@LK@3vcc-io-sd-regulatorregulator-fixed Kvccio_sdvw@2ZYvccio-wl-regulatorregulator-fixed Kvccio_wlv2Z2ZYvdd-10-regulatorregulator-fixedKvdd_10vB@B@3 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-sd-highspeedcard-detect-delaypinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqmmc-hs200-1_2vmmc-hs200-1_8vnon-removable#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-namespower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codedefault-state