q8k(j,rockchip,rk3368-evb-act8846rockchip,rk3368 +&7Rockchip RK3368 EVB with ACT8846 pmicaliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/ethernet@ff290000/mmc@ff0f0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psci cpu@100cpuarm,cortex-a53pscicpu@101cpuarm,cortex-a53pscicpu@102cpuarm,cortex-a53pscicpu@103cpuarm,cortex-a53psciarm-pmuarm,armv8-pmuv3`pqrstuvw  psci arm,psci-0.2smctimerarm,armv8-timer0   oscillator fixed-clockn6 xin24m3?mmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @@р N  D r vUbiuciuciu-driveciu-samplea l sreset disabledmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc @@р N  E s wUbiuciuciu-driveciu-samplea !l sreset disabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshc@@р N  G u yUbiuciuciu-driveciu-samplea #l sresetokay default  saradc@ff100000rockchip,saradc $N I [Usaradcapb_pclkl W ssaradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spiN A RUspiclkapb_pclk ,default+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spiN B SUspiclkapb_pclk -default+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spiN C TUspiclkapb_pclk )default+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2c >+Ui2cN Ndefault disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2c ?+Ui2cN Odefault disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2c @+Ui2cN Pdefault disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2c A+Ui2cN Qdefault disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartn6N M UUbaudclkapb_pclk 7 disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartn6N N VUbaudclkapb_pclk 8 disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartn6N P XUbaudclkapb_pclk : disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartn6N Q YUbaudclkapb_pclk ; disableddma-controller@ff250000arm,pl330arm,primecell%@"N  Uapb_pclkthermal-zonescpu-thermal9dO]tripscpu_alert0m$ypassive cpu_alert1m8ypassive!cpu_critmsy criticalcooling-mapsmap0 0map1!0 gpu-thermal9dO]tripsgpu_alert0m8ypassive"gpu_critm8y criticalcooling-mapsmap0"0tsadc@ff280000rockchip,rk3368-tsadc( %N H ZUtsadcapb_pclkl  stsadc-apbinitdefaultsleep#$#sokayethernet@ff290000rockchip,rk3368-gmac)  macirq%8N  f g c ]MUstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macokay(&3rmiiP*syr828@41silergy,syr828Avdd_gpu Pp*P*act8846@5aactive-semi,act8846Zokay[*f*q*|*+*,regulatorsREG1VCC_DDROO*REG2VCC_IO2Z2Z*+REG3VDD_LOG ``*REG4VCC_20*,REG5 VCCIO_SDw@2Z*REG6 VDD10_LCDB@B@*REG7 VCCA_CODEC2Z2Z*REG8VCCA_TP2Z2Z*REG9 VCCIO_PMU2Z2Z*REG10VDD_10B@B@*REG11VCC_18w@w@*REG12 VCC18_LCDw@w@*i2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cf =+Ui2cN Mdefault- disabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault.N _okayLpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmhdefault/N _ disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmh N _ disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmh0default0N _ disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uartiN O WUbaudclkapb_pclk 9default1okaymbox@ff6b0000rockchip,rk3368-mailboxk0N E Upclk_mailbox disabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdspower-controller!rockchip,rk3368-power-controller+Cpower-domain@12 N       c h g n o r s f d d h i l k j n m$23456789:power-domain@14 N  o p ;<=power-domain@16N @>syscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdsDio-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-modeRBRBRB RBclock-controller@ff760000rockchip,rk3368-cruvN?Uxin24m%3 syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdw%io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdtN p Ookaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timer  BN a U Upclktimerspdif@ff880000rockchip,rk3368-spdif 6N S  Umclkhclk'@,txdefaultA disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2s (Ui2s_clki2s_hclkN T '@@,txrx disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2s 5Ui2s_clki2s_hclkN R '@@,txrxdefaultB disablediommu@ff900800rockchip,iommu N  Uaclkiface6C D disablediommu@ff914000rockchip,iommu @P N  UaclkifaceD6C Q disablediommu@ff930300rockchip,iommu N  Uaclkiface6C D disablediommu@ff9a0440rockchip,iommu @@@ N  UaclkifaceD disablediommu@ff9a0800rockchip,iommu  N  UaclkifaceD disabledqos@ffad0000rockchip,rk3368-qossyscon 2qos@ffad0080rockchip,rk3368-qossyscon 3qos@ffad0100rockchip,rk3368-qossyscon 4qos@ffad0180rockchip,rk3368-qossyscon 5qos@ffad0200rockchip,rk3368-qossyscon 6qos@ffad0280rockchip,rk3368-qossyscon 7qos@ffad0300rockchip,rk3368-qossyscon 8qos@ffad0380rockchip,rk3368-qossyscon 9qos@ffad0400rockchip,rk3368-qossyscon :qos@ffae0000rockchip,rk3368-qossyscon ;qos@ffae0100rockchip,rk3368-qossyscon <qos@ffae0180rockchip,rk3368-qossyscon =qos@ffaf0000rockchip,rk3368-qossyscon >efuse@ffb00000rockchip,rk3368-efuse +N q Upclk_efusecpu-leakage@17temp-adjust@1finterrupt-controller@ffb71000 arm,gic-400l@ @ `   pinctrlrockchip,rk3368-pinctrl%D+gpio@ff750000rockchip,gpio-bankuN @ QlJgpio@ff780000rockchip,gpio-bankxN A Rlgpio@ff790000rockchip,gpio-bankyN B SlNgpio@ff7a0000rockchip,gpio-bankzN C Tl'pcfg-pull-upGpcfg-pull-downpcfg-pull-noneHpcfg-pull-none-12ma Iemmcemmc-clkE emmc-cmdF emmc-pwrGemmc-bus1Gemmc-bus4@GGGGemmc-bus8FFFFFFFFemmc-resetHMgmacrgmii-pinsHHHI I III IHHHHHHrmii-pinsHHHI I IHHHH(i2c0i2c0-xfer HH)i2c1i2c1-xfer HH-i2c2i2c2-xfer  HHi2c3i2c3-xfer HHi2c4i2c4-xfer HHi2c5i2c5-xfer HHi2si2s-8ch-bus H HHHHHHHHBpwm0pwm0-pinH.pwm1pwm1-pinH/pwm3pwm3-pinH0sdio0sdio0-bus1Gsdio0-bus4@GGGGsdio0-cmdGsdio0-clkHsdio0-cdGsdio0-wpGsdio0-pwrGsdio0-bkpwrGsdio0-intGsdmmcsdmmc-clk Hsdmmc-cmd Gsdmmc-cd Gsdmmc-bus1Gsdmmc-bus4@GGGGspdifspdif-txHAspi0spi0-clkGspi0-cs0Gspi0-cs1Gspi0-txGspi0-rxGspi1spi1-clkGspi1-cs0Gspi1-cs1Gspi1-rxGspi1-txGspi2spi2-clk Gspi2-cs0 Gspi2-rx Gspi2-tx Gtsadcotp-pinH#otp-outH$uart0uart0-xfer GHuart0-ctsHuart0-rtsHuart1uart1-xfer GHuart1-ctsHuart1-rtsHuart2uart2-xfer GH1uart3uart3-xfer GHuart3-ctsHuart3-rtsHuart4uart4-xfer GHuart4-ctsHuart4-rtsHpcfg-pull-none-drv-8maEpcfg-pull-up-drv-8maFbacklightbl-enHKkeyspwr-keyGOpmicpmic-intGsdiowifi-reg-onHbt-rstHusbhost-vbus-drvHPchosenserial2:115200n8memorymemory@backlightpwm-backlight  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~& ?JdefaultKLLB@emmc-pwrseqmmc-pwrseq-emmcMdefault QN gpio-keys gpio-keysdefaultOkey-power] FJ kGPIO Powerqtvcc-host-regulatorregulator-fixed| TJdefaultP vcc_host*>P*vcc-lan-regulatorregulator-fixedvcc_lan2Z2Z*>P+&vcc-sys-regulatorregulator-fixedvcc_sysLK@LK@*>* compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedmmc-pwrseqnon-removablepinctrl-namespinctrl-0#io-channel-cellsreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplyvp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-namespower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathbrightness-levelsdefault-brightness-levelenable-gpiospwmsreset-gpioswakeup-sourcelabellinux,codeenable-active-high