}V8v(^v&firefly,roc-rk3308-ccrockchip,rk3308 +7Firefly ROC-RK3308-CC boardaliases=/pinctrl/gpio@ff220000C/pinctrl/gpio@ff230000I/pinctrl/gpio@ff240000O/pinctrl/gpio@ff250000U/pinctrl/gpio@ff260000[/i2c@ff040000`/i2c@ff050000e/i2c@ff060000j/i2c@ff070000o/serial@ff0a0000w/serial@ff0b0000/serial@ff0c0000/serial@ff0d0000/serial@ff0e0000/spi@ff120000/spi@ff130000/spi@ff140000/mmc@ff480000/mmc@ff490000cpus+cpu@0cpuarm,cortex-a35psciZ"3>cpu@1cpuarm,cortex-a35psci">cpu@2cpuarm,cortex-a35psci"> cpu@3cpuarm,cortex-a35psci"> idle-statesFpscicpu-sleeparm,idle-stateSd{x>l2-cachecache>opp-table-0operating-points-v2>opp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock" 2mac_clkinEpsci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clockE"n62xin24m>Rgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd>Nreboot-modesyscon-reboot-modeRYRBiRBuRBRBRB syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd@+usb2phy@100rockchip,rk3308-usb2phy Hphyclk 2usb480m_phyE disabled> otg-port$CDEotg-bvalidotg-idlinestate disabled>:host-port J linestate disabled>;syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default +okay"rtc@51 nxp,pcf8563QEi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+ disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk default+ disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclk default  disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclk default  disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclk defaultokayserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclk default disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart baudclkapb_pclk default  disabledspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk!&txrxdefault disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk!&txrxdefault !"# disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk!$$&txrxdefault%&'( disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault)0 disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault*0 disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y pwmpclkdefault+0 disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y pwmpclkdefault,0 disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault-0 disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkactive.0okay>`pwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x pwmpclkdefault/0 disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x pwmpclkdefault00 disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault10okay>epwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault20 disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  pwmpclkdefault30 disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 pwmpclkdefault40 disabledrktimer@ff1a0000rockchip,rk3288-timer   pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%saradcapb_pclk;MF Tsaradc-apb disableddma-controller@ff2c0000arm,pl330arm,primecell,@` apb_pclkw>dma-controller@ff2d0000arm,pl330arm,primecell-@` apb_pclkw>$i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\i2s_clki2s_hclk!$$ &txrxMTreset-mreset-hdefault5678 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^i2s_clki2s_hclk!$ &rxMTreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b mclkhclk!$ &txdefault9 disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2@ Botgotg@ : usb2-phy disabledusb@ff440000 generic-ehciD G ;usb disabledusb@ff450000 generic-ohciE H ;usb disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012biuciuciu-driveciu-sampleрdefault<=>?okay,!.;I@UAmmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<biuciuciu-driveciu-sampleрokaybqmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567biuciuciu-driveciu-sampleрdefault BCD disablednand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcK@ Q-ahbnfc-рEFGHIJKdefault disabledethernet@ff4e0000rockchip,rk3308-gmacN @macirq@@BBA@C[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedrmiidefaultLMM} TstmmacethN disabledspi@ff4c0000 rockchip,sfcL@ R=clk_sfchclk_sfc OPQdefault disabledclock-controller@ff500000rockchip,rk3308-cruPRxin24mNE>interrupt-controller@ff580000 arm,gic-400@XX X@ X`   >sram@fff80000 mmio-sram+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrlN+defaultSgpio@ff220000rockchip,gpio-bank" (>^gpio@ff230000rockchip,gpio-bank# )gpio@ff240000rockchip,gpio-bank$ *gpio@ff250000rockchip,gpio-bank% +gpio@ff260000rockchip,gpio-bank& ,>cpcfg-pull-up>]pcfg-pull-down >Zpcfg-pull-none>Vpcfg-pull-none-2ma)pcfg-pull-up-2ma)pcfg-pull-up-4ma)>\pcfg-pull-none-4ma)>[pcfg-pull-down-4ma )pcfg-pull-none-8ma)>Tpcfg-pull-up-8ma)>Upcfg-pull-none-12ma) >Xpcfg-pull-up-12ma) >Wpcfg-pull-none-smt8>Ypcfg-output-highMpcfg-output-lowYpcfg-input-highdpcfg-inputdemmcemmc-clkq Temmc-cmdqUemmc-pwrenq Vemmc-rstnq Vemmc-bus1qUemmc-bus4@qUUUUemmc-bus8qUUUUUUUUflashflash-csn0q V>Hflash-rdyq V>Jflash-aleq V>Eflash-cleq V>Gflash-wrnqV>Kflash-rdnq V>Iflash-bus8qWWWWWWWW>Fsfcsfc-bus4@qVVVV>Qsfc-bus2 qVVsfc-cs0qV>Psfc-clkqV>Ogmacrmii-pinsqXXXVVVVV V>Lmac-refclk-12maq X>Mmac-refclkq Vgmac-m1rmiim1-pinsqXXXVVVVV Vmacm1-refclk-12maq Xmacm1-refclkq Vi2c0i2c0-xfer qYY> i2c1i2c1-xfer q Y Y> i2c2i2c2-xfer qYY>i2c3-m0i2c3m0-xfer qYY>i2c3-m1i2c3m1-xfer q Y Yi2c3-m2i2c3m2-xfer qYYi2s_2ch_0i2s-2ch-0-mclkq Vi2s-2ch-0-sclkq V>5i2s-2ch-0-lrckqV>6i2s-2ch-0-sdoqV>8i2s-2ch-0-sdiqV>7i2s_8ch_0i2s-8ch-0-mclkqVi2s-8ch-0-sclktxqVi2s-8ch-0-sclkrxqVi2s-8ch-0-lrcktxqVi2s-8ch-0-lrckrxqVi2s-8ch-0-sdo0q Vi2s-8ch-0-sdo1q Vi2s-8ch-0-sdo2q Vi2s-8ch-0-sdo3q Vi2s-8ch-0-sdi0q Vi2s-8ch-0-sdi1qVi2s-8ch-0-sdi2qVi2s-8ch-0-sdi3qVi2s_8ch_1_m0i2s-8ch-1-m0-mclkqVi2s-8ch-1-m0-sclktxqVi2s-8ch-1-m0-sclkrxqVi2s-8ch-1-m0-lrcktxqVi2s-8ch-1-m0-lrckrxqVi2s-8ch-1-m0-sdo0qVi2s-8ch-1-m0-sdo1-sdi3qVi2s-8ch-1-m0-sdo2-sdi2q Vi2s-8ch-1-m0-sdo3_sdi1q Vi2s-8ch-1-m0-sdi0q Vi2s_8ch_1_m1i2s-8ch-1-m1-mclkq Vi2s-8ch-1-m1-sclktxq Vi2s-8ch-1-m1-sclkrxqVi2s-8ch-1-m1-lrcktxqVi2s-8ch-1-m1-lrckrxqVi2s-8ch-1-m1-sdo0qVi2s-8ch-1-m1-sdo1-sdi3qVi2s-8ch-1-m1-sdo2-sdi2qVi2s-8ch-1-m1-sdo3_sdi1qVi2s-8ch-1-m1-sdi0qVpdm_m0pdm-m0-clkqVpdm-m0-sdi0q Vpdm-m0-sdi1q Vpdm-m0-sdi2q Vpdm-m0-sdi3qVpdm_m1pdm-m1-clkqVpdm-m1-sdi0qVpdm-m1-sdi1qVpdm-m1-sdi2qVpdm-m1-sdi3qVpdm_m2pdm-m2-clkmqVpdm-m2-clkqVpdm-m2-sdi0q Vpdm-m2-sdi1qVpdm-m2-sdi2qVpdm-m2-sdi3qVpwm0pwm0-pinq Vpwm0-pin-pull-downq Z>1pwm1pwm1-pinqV>2pwm1-pin-pull-downqZpwm2pwm2-pinqV>3pwm2-pin-pull-downqZpwm3pwm3-pinqV>4pwm3-pin-pull-downqZpwm4pwm4-pinqV>-pwm4-pin-pull-downqZpwm5pwm5-pinqVpwm5-pin-pull-downqZ>.pwm6pwm6-pinqV>/pwm6-pin-pull-downqZpwm7pwm7-pinqV>0pwm7-pin-pull-downqZpwm8pwm8-pinq V>)pwm8-pin-pull-downq Zpwm9pwm9-pinq V>*pwm9-pin-pull-downq Zpwm10pwm10-pinq V>+pwm10-pin-pull-downq Zpwm11pwm11-pinqV>,pwm11-pin-pull-downqZrtcrtc-32kqV>Ssdmmcsdmmc-clkq[><sdmmc-cmdq\>=sdmmc-detq\>>sdmmc-pwrenq[sdmmc-bus1q\sdmmc-bus4@q\\\\>?sdiosdio-clkqT>Dsdio-cmdqU>Csdio-pwrenqTsdio-wrptqTsdio-intnqTsdio-bus1qUsdio-bus4@qUUUU>Bspdif_inspdif-inqVspdif_outspdif-outqV>9spi0spi0-clkq\>spi0-csn0q\>spi0-misoq\>spi0-mosiq\>spi1spi1-clkq \> spi1-csn0q \>!spi1-misoq \>"spi1-mosiq \>#spi1-m1spi1m1-misoq\spi1m1-mosiq\spi1m1-clkq\spi1m1-csn0q \spi2spi2-clkq\>%spi2-csn0q\>&spi2-misoq\>'spi2-mosiq\>(tsadctsadc-otp-pinq Vtsadc-otp-outq Vuart0uart0-xfer q]]>uart0-ctsqV>uart0-rtsqV>uart0-rts-pinqVuart1uart1-xfer q]]>uart1-ctsqV>uart1-rtsqV>uart2-m0uart2m0-xfer q]]>uart2-m1uart2m1-xfer q]]uart3uart3-xfer q ] ]>uart3-m1uart3m1-xfer q]]uart4uart4-xfer q ]]>uart4-ctsqV>uart4-rtsqV>uart4-rts-pinqVir-receiverir-recv-pinqV>_buttonspwr-keyq]chosenserial2:1500000n8ir-receivergpio-ir-receiver ^default_ir_tx pwm-ir-tx`aleds gpio-ledsled-0firefly:red:powerir-power-clickon ^led-1firefly:blue:userir-user-clickoff ^ typec-vcc5vregulator-fixed typec_vcc5vLK@LK@>avcc5v0-sysregulator-fixed vcc5v0_sysLK@LK@%a>bvcc-ioregulator-fixedvcc_io2Z2Z%b>dvcc-sdmmcregulator-gpio vcc_sdmmcw@2Z ^w@2Z%b>Avcc-sdregulator-fixed 0cvcc_sd2Z2Z%d>@vdd-corepwm-regulatore vdd_core xr`5Sb>vdd-logregulator-fixedvdd_log%b compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removableassigned-clock-ratesphy-moderockchip,grf#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathgpiospwmslabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioregulator-settling-time-up-uspwm-supply