P8D( D4mediatek,mt8395-evkmediatek,mt8395mediatek,mt8195 +"7MediaTek Genio 1200 EVK-P1V2-EMMCaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100/soc/ethernet@11021000cpus+cpu@0cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@100cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@200cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@300cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@400cpuarm,cortex-a78 psci-f=P`m@@ cpu@500cpuarm,cortex-a78 psci-f=P`m@@cpu@600cpuarm,cortex-a78 psci-f=P`m@@cpu@700cpuarm,cortex-a78 psci-f=P`m@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state2*_:Dcpu-retention-barm,idle-state-*:cpu-off-larm,idle-state7*:Hcpu-off-barm,idle-state2*:l2-cache0cacheKbo@Wl2-cache1cacheKbo@Wl3-cachecacheKb o@Wdsu-pmu arm,dsu-pmue p ufaildmic-codec dmic-codec|mt8195-sound udisabledfixed-factor-clock-13mfixed-factor-clockclk13m)oscillator-26m fixed-clock-clk26moscillator-32k fixed-clock-clk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 opp-table-gpuoperating-points-v2oopp-390000000 > hopp-410000000 p opp-431000000  opp-473000000 1h@ <opp-515000000 F <opp-556000000 !# Ҧopp-598000000 # opp-640000000 &% opp-670000000 'c opp-700000000 )' Lopp-730000000 + }opp-760000000 -L `opp-790000000 /q 4opp-820000000 05 opp-850000000 2 @opp-880000000 4s qpmu-a55arm,cortex-a55-pmu epmu-a78arm,cortex-a78-pmu epsci arm,psci-1.0smctimerarm,armv8-timer @e   soc+ simple-bus!(interrupt-controller@c000000 arm,gic-v33D [    e ppi-partitionsinterrupt-partition-0p interrupt-partition-1p syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfdysyscon@10003000mediatek,mt8195-pericfgsyscon0Bpinctrl@10005000mediatek,mt8195-pinctrlPBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint[e3audio-default-pinspins-cmd-dat4=>ABCDEFGHIJKdisp-pwm1-default-pinspins1hedp-panel-12v-en-pinspins1`edp-panel-3v3-en-pinspins1eth-default-pins>pins-ccUVWXpins-mdioYZpins-power[\pins-rxdQRSTpins-txdMNOPeth-sleep-pins?pins-ccUVWXpins-mdioYZpins-rxdQRSTpins-txdMNOPgpio-keys-pinspinsji2c0-pins\pins i2c1-pins]pins  i2c2-pins`pins  i2c6-pinsXpinsmmc0-default-pinsCpins-clkz'fpins-cmd-dat$~}|{wvutyepins-rstxemmc0-uhs-pinsDpins-clkz'fpins-cmd-dat$~}|{wvutyepins-ds'fpins-rstxemmc1-default-pinsGpins-clko'fpins-cmd-datnpqrsemmc1-uhs-pinsHpins-clko'fpins-cmd-datnpqrsemt6360-pinsYpinspcie0-default-pinsRpins pcie0-idle-pinsSpins6pcie1-default-pinsVpins pwm0-default-pins5pins-cmd-dataspi1-pins6pinsspi-pins9pinstouch-pins_pins-irqpins-resetuart0-pins0pinsbcuart1-pins1pinsdefgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+A,power-domain@8+AUpower-domain@9 cmfgalto+Apower-domain@10 Apower-domain@11 Apower-domain@12 Apower-domain@13 Apower-domain@14Apower-domain@15 @AK   cvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18o+Apower-domain@24cvdec1-0oApower-domain@27 cvenc1-larboApower-domain@168$%&'()Dcvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5o+Apower-domain@17cvppsys1vppsys1-0vppsys1-1oApower-domain@22     $cwepsys-0wepsys-1wepsys-2wepsys-3oApower-domain@23!cvdec0-0oApower-domain@25"cvdec2-0oApower-domain@26# cvenc0-larboApower-domain@18 $$$&cvdosys1vdosys1-0vdosys1-1vdosys1-2o+Apower-domain@19oApower-domain@20oApower-domain@21Qchdmi_txApower-domain@28%%  cimg-0img-1o+Apower-domain@29Apower-domain@30%&cipeipe-0ipe-1oApower-domain@31('''''ccam-0cam-1cam-2cam-3cam-4o+Apower-domain@32 Apower-domain@33!Apower-domain@34"Apower-domain@0oApower-domain@1oApower-domain@2Apower-domain@3Apower-domain@457ccsi_rx_topcsi_rx_top1Apower-domain@5( cetherApower-domain@6Xn cadspadsp1+oApower-domain@7 g"n2caudioaudio1audio2audio3oAwatchdog@10007000mediatek,mt8195-wdtpy/syscon@1000c000"mediatek,mt8195-apmixedsyssyscontimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerpe )pwrap@10024000mediatek,mt8195-pwrapsyscon@pwrape cspiwrap$pmicmediatek,mt6359[3 mt6359codecregulatorsbuck_vs1vs1 57!Okbuck_vgpu11vgpu1177O kbuck_vmodemvmodem7*Obuck_vpuvpu77O kbuck_vcorevcore7 O kbuck_vs2vs2 57jOkbuck_vpavpa 77O,buck_vproc2vproc277LO buck_vproc1vproc177LO buck_vcore_sshub vcore_sshub77buck_vgpu11_sshub vgpu11_sshub77ldo_vaud18vaud18w@7w@Okldo_vsim1vsim17/M`ldo_vibrvibrO72Zldo_vrf12vrf127 kldo_vusbvusb-7-OkLldo_vsram_proc2 vsram_proc2 7LOkldo_vio18vio187Okldo_vcamiovcamio7kldo_vcn18vcn18w@7w@Oldo_vfe28vfe28*7*Oxldo_vcn13vcn13 7 ldo_vcn33_1_bt vcn33_1_bt*75gldo_vcn33_1_wifi vcn33_1_wifi*75gldo_vaux18vaux18w@7w@Okldo_vsram_others vsram_others 7Oldo_vefusevefuse7ldo_vxo22vxo22w@7!kldo_vrfckvrfck`7ldo_vrfck_1vrfck7jldo_vbif28vbif28*7*Oldo_vio28vio28*72Zkldo_vemcvemc,@ 72Zldo_vemc_1vemc&%72ZEldo_vcn33_2_bt vcn33_2_bt2Z72Z8ldo_vcn33_2_wifi vcn33_2_wifi*75gldo_va12va12O7 kldo_va09va09 57Oldo_vrf18vrf187Pldo_vsram_md vsram_md 7*Oldo_vufsvufs7Fldo_vm18vm187kldo_vbbckvbbck7Okldo_vsram_proc1 vsram_proc1 7LOkldo_vsim2vsim27/M`ldo_vsram_others_sshubvsram_others_sshub 7mt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi p pmifspmimstE(cpmif_sys_ckpmif_tmr_ckspmimst_clk_mux$+pmic@6mediatek,mt6315-regulatorregulatorsvbuck1vbuck1Vbcpu77O kpmic@7mediatek,mt6315-regulatorregulatorsvbuck1vbuck1Vgpu77O infra-iommu@10315000mediatek,mt8195-iommu-infra1PPPeOmailbox@10320000mediatek,mt8195-gce2@emailbox@10330000mediatek,mt8195-gce3@epscp@10500000mediatek,mt8195-scp0Prpsramcfgl1tcmeuokay*clock-controller@10720000mediatek,mt8195-scp_adspr+dsp@10803000mediatek,mt8195-dsp 0 cfgsram,Xn+#Kcadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h,rxtx-. udisabledmailbox@10816000mediatek,mt8195-adsp-mbox`e-mailbox@10817000mediatek,mt8195-adsp-mboxpe.mt8195-afe-pcm@10890000mediatek,mt8195-audio,e6/ !audiosysg"#neabcd2+cclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp udisabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbusuokay-07defaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbusuokay-17defaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc cmainE udisabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0(spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ecparent-clksel-clkspi-clk udisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap eW23$clvts-calib-data-1lvts-calib-data-2tsvs@1100bc00mediatek,mt8195-svsecmainW42(csvs-calibration-datat-calibration-data!svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwme,*0cmainmmuokay7default-5pwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwme+Ncmainmm udisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+e3cparent-clksel-clkspi-clkuokay-67default @can@0microchip,mcp2518fd71- 88spi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ e4cparent-clksel-clkspi-clkuokay-97defaultspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0e5cparent-clksel-clkspi-clk udisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+e<cparent-clksel-clkspi-clk udisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+e=cparent-clksel-clkspi-clk udisabledspi@1101d000mediatek,mt8195-spi-slaveeRcspi udisabledspi@1101e000mediatek,mt8195-spi-slaveeScspi udisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@emacirq.caxiapbmac_mainptp_refrmii_internalmac_cg0((RST( RST,:;"<5@Kuokay Xrgmii-rxida= l] |''7defaultsleep->?mdiosnps,dwmac-mdio+eth-phy0@1ethernet-phy-id001c.c916=stmmac-axi-config:rx-queues-config;queue0%queue1%queue2%queue3%tx-queues-config=S<queue0eqqueue1eqqueue2eqqueue3equsb@11200000'mediatek,mt8195-xhcimediatek,mtk-xhci   > macippce@A,-$/B$csys_ckref_ckmcu_ckdma_ckxhci_ck Bguokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #ecsourcehclksource_cguokay7defaultstate_uhs-CD  L E F *mmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $e$csourcehclksource_cguokay7defaultstate_uhs-GH  8 I V d I J *mmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %e Icsourcehclksource_cg  udisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'eW23$clvts-calib-data-1lvts-calib-data-2tusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> macippceK./$(($csys_ckref_ckmcu_ckdma_ckxhci_ck Bhuokay kLusb@112a0000'mediatek,mt8195-xhcimediatek,mtk-xhci **> macippceM01 (($csys_ckref_ckmcu_ckdma_ckxhci_ck Biuokay kLusb@112b0000'mediatek,mt8195-xhcimediatek,mtk-xhci ++> macippceN23 (( $csys_ckref_ckmcu_ckdma_ckxhci_ck Bjuokay kLpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-mace y8!  O 0V#&+K(/cpl_250mtl_26mtl_96mtl_32kperi_26mperi_memGP pcie-phy,!mac3 ` QQQQuokay 7defaultidle-RSinterrupt-controller[3Qpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-mace y8!$$ $ $  O (WXQ(/cpl_250mtl_26mtl_96mtl_32kperi_26mperi_memHT pcie-phy,!mac3 ` UUUU udisabled7default-Vinterrupt-controller[3Uspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2e9o(( cspisfaxi+ udisabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse+usb3-tx-imp@184,1 fusb3-rx-imp@184,2 eusb3-intr@185 dusb3-tx-imp@186,1 cusb3-rx-imp@186,2 busb3-intr@187 ausb2-intr-p0@188,1 usb2-intr-p1@188,2 usb2-intr-p2@189,1 usb2-intr-p3@189,2 pciephy-rx-ln1@190,1 mpciephy-tx-ln1-nmos@190,2 lpciephy-tx-ln1-pmos@191,1 kpciephy-rx-ln0@191,2 jpciephy-tx-ln0-nmos@192,1 ipciephy-tx-ln0-pmos@192,2 hpciephy-glb-intr@193 gdp-data@1aclvts1-calib@1bc2lvts2-calib@1d083svs-calib@580d4t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!uokayusb-phy@0cref Mt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!uokayusb-phy@0cref Ndsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx0_pll  udisableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx1_pll  udisabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "eW; cmaindma+ udisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "eW; cmaindma+uokay--X7defaultpmic@34mediatek,mt63604 eIRQB[3-Ychargermediatek,mt6360-chg @usb-otg-vbus-regulator usb-otg-vbusC(7Xregulatormediatek,mt6360-regulator Zbuck1 emi_vdd27  kbuck2 emi_vddq7  kZldo1 tp1_p3v02Z72Zk^ldo2 panel1_p1v8w@7w@ldo3vmc_pmuO76Jldo5 vmch_pmu)276Ildo6 mt6360_ldo1 7 ldo7 emi_vmddr_en 7 ki2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "eW; cmaindma+ udisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0Wi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "e[; cmaindma+uokay--\7defaulti2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "e[; cmaindma+uokay--]7defaulttouchscreen@5dgoodix,gt9271]    ^7default-_i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "e[; cmaindma+uokay--`7defaulti2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"e[; cmaindma+ udisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"e[; cmaindma+ udisabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wP[t-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!,uokayusb-phy@0  crefda_ref Kusb-phy@700 crefda_ref Wabccintrrx_imptx_imp Tt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!uokayusb-phy@0  crefda_ref @usb-phy@700 crefda_ref Wdefcintrrx_imptx_imp Aphy@11e80000mediatek,mt8195-pcie-physifWghijklmGcglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1, uokayPufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy cunipromp  udisabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@n0e jobmmugpu $o(, , , , , 8core0core1core2core3core4 udisabledclock-controller@13fbf000mediatek,mt8195-mfgcfgnsyscon@14000000mediatek,mt8195-vppsys0syscon Kpdma-controller@14001000mediatek,mt8195-mdp3-rdma Kp c , wq<p p ppp ~display@14002000mediatek,mt8195-mdp3-fg  Kp display@14003000mediatek,mt8195-mdp3-stitch0 Kp0display@14004000mediatek,mt8195-mdp3-hdr@ Kp@"display@14005000mediatek,mt8195-mdp3-aalPeF KpP ,display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` Kp` c% display@14007000mediatek,mt8195-mdp3-tdshpp Kpp#display@14008000mediatek,mt8195-mdp3-coloreI Kp$,display@14009000mediatek,mt8195-mdp3-ovleJ Kp%, wqdisplay@1400a000mediatek,mt8195-mdp3-padding Kp,display@1400b000mediatek,mt8195-mdp3-tcc Kpdma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot Kp c + wq, ~mutex@1400f000mediatek,mt8195-vpp-mutexeP Kp,smi@14010000mediatek,mt8195-smi-sub-commoncapbsmigals0 r,ssmi@14011000mediatek,mt8195-smi-sub-commoncapbsmigals0 r,smi@14012000mediatek,mt8195-smi-common-vpp  capbsmigals0gals1,rlarb@14013000mediatek,mt8195-smi-larb0  scapbsmi,viommu@14018000mediatek,mt8195-iommu-vpp8 tuvwxyz{|}~eRcbclk,qclock-controller@14e00000mediatek,mt8195-wpesys clock-controller@14e02000mediatek,mt8195-wpesys_vpp0 clock-controller@14e03000mediatek,mt8195-wpesys_vpp10larb@14e04000mediatek,mt8195-smi-larb@    capbsmi,larb@14e05000mediatek,mt8195-smi-larbP  r   capbsmigals,xsyscon@14f00000mediatek,mt8195-vppsys1syscon Kp mutex@14f01000mediatek,mt8195-vpp-mutexe{ Kp ',larb@14f02000mediatek,mt8195-smi-larb    capbsmigals,larb@14f03000mediatek,mt8195-smi-larb0  s capbsmigals,wdisplay@14f06000mediatek,mt8195-mdp3-split` Kp `+,,display@14f07000mediatek,mt8195-mdp3-tccp Kp pdma-controller@14f08000mediatek,mt8195-mdp3-rdma Kp  c w, ~dma-controller@14f09000mediatek,mt8195-mdp3-rdma Kp  c  w, ~dma-controller@14f0a000mediatek,mt8195-mdp3-rdma Kp  c  wq, ~display@14f0b000mediatek,mt8195-mdp3-fg Kp  display@14f0c000mediatek,mt8195-mdp3-fg Kp  display@14f0d000mediatek,mt8195-mdp3-fg Kp  display@14f0e000mediatek,mt8195-mdp3-hdr Kp display@14f0f000mediatek,mt8195-mdp3-hdr Kp display@14f10000mediatek,mt8195-mdp3-hdr Kp  display@14f11000mediatek,mt8195-mdp3-aalei Kp ,display@14f12000mediatek,mt8195-mdp3-aal ej Kp ,display@14f13000mediatek,mt8195-mdp3-aal0ek Kp 0!,display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz@ Kp @ cdisplay@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszP Kp P c$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` Kp ` c%display@14f17000mediatek,mt8195-mdp3-tdshpp Kp pdisplay@14f18000mediatek,mt8195-mdp3-tdshp Kp (display@14f19000mediatek,mt8195-mdp3-tdshp Kp )display@14f1a000mediatek,mt8195-mdp3-merge Kp ,display@14f1b000mediatek,mt8195-mdp3-merge Kp ,display@14f1c000mediatek,mt8195-mdp3-coloret Kp ,display@14f1d000mediatek,mt8195-mdp3-color Kp eu,display@14f1e000mediatek,mt8195-mdp3-colorev Kp ,display@14f1f000mediatek,mt8195-mdp3-ovlew Kp , wdisplay@14f20000mediatek,mt8195-mdp3-padding Kp ,display@14f21000mediatek,mt8195-mdp3-padding Kp ,display@14f22000mediatek,mt8195-mdp3-padding  Kp ,dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot0 Kp 0 c w, ~dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot@ Kp @ c w, ~dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotP Kp P c wq, ~clock-controller@15000000mediatek,mt8195-imgsys%larb@15001000mediatek,mt8195-smi-larb  %%%  capbsmigals,smi@15002000mediatek,mt8195-smi-sub-common %%capbsmigals0 r,smi@15003000mediatek,mt8195-smi-sub-common0%%% capbsmigals0 ,clock-controller@15110000 mediatek,mt8195-imgsys1_dip_toplarb@15120000mediatek,mt8195-smi-larb  %capbsmi,clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrclock-controller@15220000mediatek,mt8195-imgsys1_wpe"larb@15230000mediatek,mt8195-smi-larb#  %capbsmi,clock-controller@15330000mediatek,mt8195-ipesys3&larb@15340000mediatek,mt8195-smi-larb4  &&capbsmi,yclock-controller@16000000mediatek,mt8195-camsys'larb@16001000mediatek,mt8195-smi-larb  ''' capbsmigals,larb@16002000mediatek,mt8195-smi-larb   ''capbsmi,zsmi@16004000mediatek,mt8195-smi-sub-common@'''capbsmigals0 ,smi@16005000mediatek,mt8195-smi-sub-commonP''capbsmigals0 r,larb@16012000mediatek,mt8195-smi-larb   capbsmi, {larb@16013000mediatek,mt8195-smi-larb0  capbsmi, larb@16014000mediatek,mt8195-smi-larb@  capbsmi,!larb@16015000mediatek,mt8195-smi-larbP  capbsmi,!clock-controller@1604f000mediatek,mt8195-camsys_rawaclock-controller@1606f000mediatek,mt8195-camsys_yuvaclock-controller@1608f000mediatek,mt8195-camsys_rawbclock-controller@160af000mediatek,mt8195-camsys_yuvb clock-controller@16140000mediatek,mt8195-camsys_mrawlarb@16141000mediatek,mt8195-smi-larb  '' capbsmigals,"larb@16142000mediatek,mt8195-smi-larb   capbsmi,"clock-controller@17200000mediatek,mt8195-ccusys larb@17201000mediatek,mt8195-smi-larb   capbsmi,|video-codec@18000000mediatek,mt8195-vcodec-dec  w+ @!`video-codec@2000mediatek,mtk-vcodec-lat-soc  wqq A!!cselvdeclattopA,video-codec@10000mediatek,mtk-vcodec-late0 w A!!cselvdeclattopA,video-codec@25000mediatek,mtk-vcodec-corePeP w AcselvdeclattopA,larb@1800d000mediatek,mt8195-smi-larb  !!capbsmi,larb@1800e000mediatek,mt8195-smi-larb  !capbsmi,clock-controller@1800f000mediatek,mt8195-vdecsys_soc!larb@1802e000mediatek,mt8195-smi-larb  capbsmi,clock-controller@1802f000mediatek,mt8195-vdecsyslarb@1803e000mediatek,mt8195-smi-larb  "capbsmi,~clock-controller@1803f000mediatek,mt8195-vdecsys_core1"clock-controller@190f3000mediatek,mt8195-apusys_pll0clock-controller@1a000000mediatek,mt8195-vencsys#larb@1a010000mediatek,mt8195-smi-larb  ##capbsmi,video-codec@1a020000mediatek,mt8195-vcodec-encH w`abcdvwxyeU # cvenc_sel@,+jpgdec-mastermediatek,mt8195-jpgdec,0 wmnrstu+!jpgdec@1a040000mediatek,mt8195-jpgdec-hw0 wmnrstueW#cjpgdec,jpgdec@1a050000mediatek,mt8195-jpgdec-hw0 wmnrstueX#cjpgdec,jpgdec@1b040000mediatek,mt8195-jpgdec-hw0 wqqqqqqe\cjpgdec,clock-controller@1b000000mediatek,mt8195-vencsys_core1syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon  Kjpgenc-mastermediatek,mt8195-jpgenc, wqqqq+!jpgenc@1a030000mediatek,mt8195-jpgenc-hw wghileV#cjpgenc,jpgenc@1b030000mediatek,mt8195-jpgenc-hw wqqqqe[cjpgenc,larb@1b010000mediatek,mt8195-smi-larb  r  capbsmigals,}ovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovle|, w Krdma@1c002000mediatek,mt8195-disp-rdma e~, w K color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0e, K0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@e, K@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalPe, KPgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`e, K`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherpe,  Kpdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsie,*cenginedigitalhs dphy udisableddsc@1c009000mediatek,mt8195-disp-dsce, Kdsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi e,+cenginedigitalhs dphy udisabledmerge@1c014000mediatek,mt8195-disp-merge@e, K@dp-intf@1c015000mediatek,mt8195-dp-intfPe,cenginepixelpll udisabledmutex@1c016000mediatek,mt8195-disp-mutex`e, K` cUlarb@1c018000mediatek,mt8195-smi-larb  ((  capbsmigals,larb@1c019000mediatek,mt8195-smi-larb  r(  capbsmigals,tsyscon@1c100000mediatek,mt8195-vdosys1syscon  Ky$smi@1c01b000mediatek,mt8195-smi-common-vdo %&)$capbsmigals0gals1,iommu@1c01f000mediatek,mt8195-iommu-vdo8 e'cbclk,mutex@1c101000mediatek,mt8195-disp-mutex vdo1_mutexe,$ cvdo1_mutex K clarb@1c102000mediatek,mt8195-smi-larb   $$$ capbsmigals,larb@1c103000mediatek,mt8195-smi-larb0  r$$  capbsmigals,udma-controller@1c104000mediatek,mt8195-vdo1-rdma@e$, w@ K@ ~dma-controller@1c105000mediatek,mt8195-vdo1-rdmaPe$, wq` KP ~dma-controller@1c106000mediatek,mt8195-vdo1-rdma`e$, wA K` ~dma-controller@1c107000mediatek,mt8195-vdo1-rdmape$, wqa Kp ~dma-controller@1c108000mediatek,mt8195-vdo1-rdmae$, wB K ~dma-controller@1c109000mediatek,mt8195-vdo1-rdmae$, wqb K ~dma-controller@1c10a000mediatek,mt8195-vdo1-rdmae$, wC K ~dma-controller@1c10b000mediatek,mt8195-vdo1-rdmae$, wqc K ~vpp-merge@1c10c000mediatek,mt8195-disp-mergee$ $cmergemerge_async, K $vpp-merge@1c10d000mediatek,mt8195-disp-mergee$ $cmergemerge_async, K $vpp-merge@1c10e000mediatek,mt8195-disp-mergee$ $cmergemerge_async, K $vpp-merge@1c10f000mediatek,mt8195-disp-mergee$ $cmergemerge_async, K $vpp-merge@1c110000mediatek,mt8195-disp-mergee$ $cmergemerge_async, K $dp-intf@1c113000mediatek,mt8195-dp-intf0e,$$/cenginepixelpll udisabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp K@Pph$%$ $#$!$$$"$1$&$'$($)$*cmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top, wqdqee($3$4$5$6$7E!vdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-txPWcdp_calibration_data,e  udisableddp-tx@1c600000mediatek,mt8195-dp-tx`Wcdp_calibration_data,e  udisabledthermal-zonescpu0-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcooling-mapsmap0 J0 O cpu1-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcooling-mapsmap0 J0 O cpu2-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcooling-mapsmap0 J0 O cpu3-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcooling-mapsmap0 J0 O cpu4-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcooling-mapsmap0 J0 O cpu5-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcooling-mapsmap0 J0 O cpu6-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcooling-mapsmap0 J0 O cpu7-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcooling-mapsmap0 J0 O vpu0-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalvpu1-thermal   # tripstrip-alert 3L ?passivetrip-crit 3 ? criticalgpu0-thermal   # tripstrip-alert 3L ?passivetrip-crit 3 ? criticalgpu1-thermal   # tripstrip-alert 3L ?passivetrip-crit 3 ? criticalvdec-thermal   # tripstrip-alert 3L ?passivetrip-crit 3 ? criticalimg-thermal   # tripstrip-alert 3L ?passivetrip-crit 3 ? criticalinfra-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcam0-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalcam1-thermal   #tripstrip-alert 3L ?passivetrip-crit 3 ? criticalchosen ^serial0:921600n8firmwareopteelinaro,optee-tzsmcmemory@40000000memory@reserved-memory+!optee@43200000 jC memory@50000000shared-dma-poolP j*memory@53000000shared-dma-poolS@memory@54600000 jT` memory@60000000shared-dma-pool` jmemory@62000000shared-dma-poolb@backlight-lcd0pwm-backlight q  v/   @backlight-lcd1pwm-backlight q  v.   @can-clk fixed-clock-1-can-clk7regulator-0regulator-fixededp_panel_3v32Z72Z  w7default-regulator-1regulator-fixededp_backlight_12v7  w`7default-gpio-keys gpio-keysbutton-volume-up d j volume_up sregulator-2regulator-fixed wifi_3v32Z72Z w k compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0ethernet0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxoutput-highdrive-strengthinput-enableinput-disablebias-disablebias-pull-updrive-strength-microampbias-pull-downoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedmediatek,mic-type-0mediatek,mic-type-1mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsmemory-regionpower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-0pinctrl-names#io-channel-cellsnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectcs-gpiosspi-max-frequencyvdd-supplyxceiver-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlesnps,reset-gpiosnps,reset-delays-usmediatek,tx-delay-psmediatek,mac-wolpinctrl-1snps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupwakeup-sourcebus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcvusb33-supplybus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN3-supplyirq-gpiosreset-gpiosAVDD28-supplyoperating-points-v2power-domain-namesmediatek,gce-client-regmediatek,gce-eventsiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsmediatek,scpmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathno-mappwmsenable-gpiosbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-active-highdebounce-intervallabellinux,code