m8_x(._@Dgoogle,tomato-rev4google,tomato-rev3google,tomatomediatek,mt8195 +7Acer Tomato (rev3 - 4) boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/i2c@11e00000/soc/i2c@11e01000/soc/i2c@11e02000/soc/i2c@11e03000/soc/i2c@11e04000/soc/i2c@11d00000/soc/i2c@11d02000 /soc/mmc@11230000/soc/mmc@11240000/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@100cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@200cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@300cpuarm,cortex-a55*.psci<Pec3@`4s@@cpu@400cpuarm,cortex-a78*.psci<Pf`s@@  cpu@500cpuarm,cortex-a78*.psci<Pf`s@@  cpu@600cpuarm,cortex-a78*.psci<Pf`s@@  cpu@700cpuarm,cortex-a78*.psci<Pf`s@@  cpu-mapcluster0core0 core1 core2 core3core4core5core6core7idle-statespscicpu-retention-larm,idle-state6G2X_hDcpu-retention-barm,idle-state6G-Xhcpu-off-larm,idle-state6G7XhHcpu-off-barm,idle-state6G2Xhl2-cache0cachey@l2-cache1cachey@ l3-cachecachey @dsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-soundokay}DL10_FEDPTX_BEETDM1_IN_BEETDM2_IN_BEETDM1_OUT_BEETDM2_OUT_BEUL_SRC1_BEAFE_SOF_DL2AFE_SOF_DL3AFE_SOF_UL4AFE_SOF_UL5default%mediatek,mt8195_mt6359_rt1019_rt56827m8195_r1019_5682sfixed-factor-clock-13mfixed-factor-clock%/:clk13m/oscillator-26m fixed-clockP:clk26moscillator-32k fixed-clockP:clk32kperformance-controller@11bc10mediatek,cpufreq-hw * 0 Mopp-table-gpuoperating-points-v2gyopp-390000000r>y hopp-410000000rpy opp-431000000ry opp-473000000r1h@y <opp-515000000rFy <opp-556000000r!#y Ҧopp-598000000r#y opp-640000000r&%y opp-670000000r'cy opp-700000000r)'y Lopp-730000000r+y }opp-760000000r-Ly `opp-790000000r/qy 4opp-820000000r05y opp-850000000r2y @opp-880000000r4sy qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.05smctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  *    ppi-partitionsinterrupt-partition-0 interrupt-partition-1syscon@10000000 mediatek,mt8195-topckgensyscon*syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd*syscon@10003000mediatek,mt8195-pericfgsyscon*0Epinctrl@10005000mediatek,mt8195-pinctrl*PB iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint&2>default>bI2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOaudio-default-pinspins-cmd-datDrEFGHIJK<12345pins-hp-jack-int-odlrYyecr50-irq-default-pinshpins-gsc-ap-int-odlrXycros-ec-irq-default-pins;pins-ec-ap-int-odlreyedptx-default-pinspins-cmd-datrdisp-pwm0-default-pins?pins-disp-pwmrRadptx-default-pinspins-cmd-datri2c0-default-pins_pins-busr i2c1-default-pins`pins-busr  i2c2-default-pinscpins-busr  i2c3-default-pinsgpins-busri2c4-default-pinsipins-busri2c5-default-pins[pins-busri2c7-default-pins\pins-busrmmc0-default-pinsHpins-cmd-dat$r~}|{wvutyyepins-clkrzfpins-rstrxemmc0-uhs-pinsIpins-cmd-dat$r~}|{wvutyyepins-clkrzfpins-dsrfpins-rstrxemmc1-detect-pinsMpins-insertr6mmc1-default-pinsLpins-cmd-datrnpqrsyepins-clkrofnor-default-pinsYpins-ck-io rpins-csrpcie0-default-pinspins-bus rpcie1-default-pinsXpins-bus rpanel-pwr-default-pinspins-vreg-enr7pio-default-pinspins-wifi-enabler:pins-low-power-pd,r./0ABCDypins-low-power-pupd<rMNOPSUZ[]^_`hikyepins-low-power-hdmi-disabler !"#ypins-low-power-pcie0-disable ryrt1019p-default-pinspins-amp-sdbrdscp-default-pins1pins-vreqrLyspi0-default-pins:pins-cs-mosi-clk rpins-misorsubpmic-default-pins]pins-subpmic-int-nrytrackpad-default-pinsapins-int-nrytouchscreen-default-pinsjpins-int-nr\yepins-rstr8pins-report-swr9syscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd*`power-controller!mediatek,mt8195-power-controller+3power-domain@8*+power-domain@9* mfgalt+ power-domain@10* power-domain@11* power-domain@12* power-domain@13* power-domain@14*power-domain@15* @AK! ! !!!!!!!!!!!!!!!!! vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+power-domain@24*"vdec1-0power-domain@27*# venc1-larbpower-domain@16*8$$$%$&$'$($)Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+power-domain@17*%%vppsys1vppsys1-0vppsys1-1power-domain@22* &&&&$wepsys-0wepsys-1wepsys-2wepsys-3power-domain@23*'vdec0-0power-domain@25*(vdec2-0power-domain@26*) venc0-larbpower-domain@18* ***&vdosys1vdosys1-0vdosys1-1vdosys1-2+power-domain@19*power-domain@20*power-domain@21*Qhdmi_txpower-domain@28*++  img-0img-1+power-domain@29*power-domain@30*+,ipeipe-0ipe-1power-domain@31*(-----cam-0cam-1cam-2cam-3cam-4+power-domain@32* power-domain@33*!power-domain@34*"power-domain@0*power-domain@1*power-domain@2*power-domain@3*power-domain@4*57csi_rx_topcsi_rx_top1power-domain@5*. etherpower-domain@6*Xn adspadsp1+power-domain@7* g"n2audioaudio1audio2audio3watchdog@10007000mediatek,mt8195-wdt*p8syscon@1000c000"mediatek,mt8195-apmixedsyssyscon*timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer*p /pwrap@10024000mediatek,mt8195-pwrapsyscon*@ pwrap spiwrap-$=pmicmediatek,mt6359 Tmt6359codech{regulatorsbuck_vs1vs1 5!buck_vgpu11vgpu117 buck_vmodemvmodem*buck_vpuvpu7 buck_vcorevcore  buck_vs2vs2 5jbuck_vpavpa 7,buck_vproc2vproc27L buck_vproc1vproc17L buck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshubdpdpldo_vaud18vaud18w@w@ldo_vsim1vsim1/M`ldo_vibrvibrO2Zldo_vrf12vrf12 ldo_vusbvusb--Fldo_vsram_proc2 vsram_proc2 Lldo_vio18vio18dldo_vcamiovcamioldo_vcn18vcn18w@w@ldo_vfe28vfe28**xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@ldo_vsram_others vsram_others q q ldo_vefusevefuseldo_vxo22vxo22w@!ldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**ldo_vio28vio28*2Zldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2ZJldo_vcn33_2_bt vcn33_2_bt*5gldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O ldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md *ldo_vufsvufsKldo_vm18vm18ldo_vbbckvbbckOldo_vsram_proc1 vsram_proc1 Lldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub mt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi *p  pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux-$=+mt6315@6mediatek,mt6315-regulator*regulatorsvbuck1+vbuck1Vbcpu7j  mt6315@7mediatek,mt6315-regulator*regulatorsvbuck1+vbuck1Vgpu7j infra-iommu@10315000mediatek,mt8195-iommu-infra*1PPP@Smailbox@10320000mediatek,mt8195-gce*2@Mmailbox@10330000mediatek,mt8195-gce*3@Mzscp@10500000mediatek,mt8195-scp0*Prp sramcfgl1tcmokayYmediatek/mt8195/scp.imgg0default1cros-ec-rpmsggoogle,cros-ec-rpmsgucros-ec-rpmsgclock-controller@10720000mediatek,mt8195-scp_adsp*r2dsp@10803000mediatek,mt8195-dsp *0  cfgsram,Xn2#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h3rxtx45okayg67mailbox@10816000mediatek,mt8195-adsp-mboxM*`4mailbox@10817000mediatek,mt8195-adsp-mboxM*p5mt8195-afe-pcm@10890000mediatek,mt8195-audio*368 audiosysg"#neabcd22clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodspokayg9serial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbusokayserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc* mainokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon*0.spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+*parent-clksel-clkspi-clkokaydefault:!ec@0+google,cros-ec-spi* Tdefault;5-keyboard-backlightgoogle,cros-kbd-led-backlighti2c-tunnelgoogle,cros-ec-i2c-tunnelG+sbs-battery@bsbs,sbs-battery* Ymregulator@0google,cros-ec-regulator*mt_pmic_vmc_ldoO6Oregulator@1google,cros-ec-regulator*mt_pmic_vmch_ldo)26Ntypecgoogle,cros-ec-typec+connector@0usb-c-connector*dualhostsourceconnector@1usb-c-connector*dualhostsourcekeyboard-controllergoogle,cros-ec-keyb Dtxc q rs}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g i(  thermal-sensor@1100b000mediatek,mt8195-lvts-ap* <=$lvts-calib-data-1lvts-calib-data-2"svs@1100bc00mediatek,mt8195-svs*main><(svs-calibration-datat-calibration-datasvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm*38*0mainmmokaydefault?pwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm*8+Nmainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+*3parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+* 4parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+*05parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+*<parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+*=parent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave*Rspi-= disabledspi@1101e000mediatek,mt8195-spi-slave*Sspi-= disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a*@Cmacirq.axiapbmac_mainptp_refrmii_internalmac_cg0..RST. -RST=3Sd@tAB disabledmdiosnps,dwmac-mdio+stmmac-axi-config@rx-queues-configAqueue0  !queue1  !queue2  !queue3  !tx-queues-config 9 OBqueue0 a  mqueue1 a  mqueue2 a  mqueue3 a  musb@11200000'mediatek,mt8195-xhcimediatek,mtk-xhci *  >  macippc {CD-,-=$/B$sys_ckref_ckmcu_ckdma_ckxhci_ck Eg okay  F Gmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc *#sourcehclksource_cgokay    L9    ' / 5defaultstate_uhsH CI MJ YKmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc *$$sourcehclksource_cg-=okay  f w69   'defaultstate_uhsLM CL   MN YOmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc *% Isourcehclksource_cg- = disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu*'<=$lvts-calib-data-1lvts-calib-data-2"usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci *))>  macippc {P-./=$..$sys_ckref_ckmcu_ckdma_ckxhci_ck Eh okay  F Gusb@112a0000'mediatek,mt8195-xhcimediatek,mtk-xhci ***>  macippc {Q-01= ..$sys_ckref_ckmcu_ckdma_ckxhci_ck Ei okay F Gusb@112b0000'mediatek,mt8195-xhcimediatek,mtk-xhci *++>  macippc {R-23= .. $sys_ckref_ckmcu_ckdma_ckxhci_ck Ej okay  F Gpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+*/@  pcie-mac 8  S 0V#&+K./pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem-G= {T pcie-phy3mac ` UUUU disabledinterrupt-controllerUpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+*/@  pcie-mac 8$$ $ $  S (WXQ./pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem-H= {V pcie-phy3mac ` WWWWokaydefaultXinterrupt-controllerWspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor*29o.. spisfaxi+okaydefaultYflash@0jedec,spi-nor*5u  efuse@11c10000%mediatek,mt8195-efusemediatek,efuse*+usb3-tx-imp@184,1* #pusb3-rx-imp@184,2* #ousb3-intr@185* #nusb3-tx-imp@186,1* #musb3-rx-imp@186,2* #lusb3-intr@187* #kusb2-intr-p0@188,1* #usb2-intr-p1@188,2* #usb2-intr-p2@189,1* #usb2-intr-p3@189,2* #pciephy-rx-ln1@190,1* #wpciephy-tx-ln1-nmos@190,2* #vpciephy-tx-ln1-pmos@191,1* #upciephy-rx-ln0@191,2* #tpciephy-tx-ln0-nmos@192,1* #spciephy-tx-ln0-pmos@192,2* #rpciephy-glb-intr@193* #qdp-data@1ac*lvts1-calib@1bc*<lvts2-calib@1d0*8=svs-calib@580*d>t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0*ref (Qt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0*ref (Rdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx* :mipi_tx0_pll ( disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx* :mipi_tx1_pll ( disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"%Z; maindma+okayPdefault[i2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"%Z; maindma+ disabledi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c * "%Z; maindma+okayPdefault\pmic@34mediatek,mt6360*4 TCIRQBdefault] clock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s*0Zi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"%^; maindma+okayPdefault_i2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"%^; maindma+okayP 30default`trackpad@15elan,ekth3000* Tdefaulta Mb i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c * "%^; maindma+okayPdefaultccodec@1a* TY X gd se frealtek,rt5682s i2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c *0"%^; maindma+okayPdefaultgtpm@50 google,cr50*P TXdefaulthi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c *@"%^; maindma+okayPdefaultitouchscreen@10 hid-over-i2c*  T\defaultj  bokayclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w*P^t-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+3okayusb-phy@0*  refda_ref (Pusb-phy@700* refda_ref klmintrrx_imptx_imp (Vt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0*  refda_ref (Cusb-phy@700* refda_ref nopintrrx_imptx_imp (Dphy@11e80000mediatek,mt8195-pcie-phy* sifqrstuvwGglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln13 ( disabledTufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy* unipromp ( disabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm*@x0 Cjobmmugpu y(3 3 3 3 3 core0core1core2core3core4okay clock-controller@13fbf000mediatek,mt8195-mfgcfg*xsyscon@14000000mediatek,mt8195-vppsys0syscon* z!dma-controller@14001000mediatek,mt8195-mdp3-rdma* z  3 3{!<z z zzz :display@14002000mediatek,mt8195-mdp3-fg*  z !display@14003000mediatek,mt8195-mdp3-stitch*0 z0!display@14004000mediatek,mt8195-mdp3-hdr*@ z@!"display@14005000mediatek,mt8195-mdp3-aal*PF zP! 3display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz*` z` %! display@14007000mediatek,mt8195-mdp3-tdshp*p zp!#display@14008000mediatek,mt8195-mdp3-color*I z!$3display@14009000mediatek,mt8195-mdp3-ovl*J z!%3 3{display@1400a000mediatek,mt8195-mdp3-padding* z!3display@1400b000mediatek,mt8195-mdp3-tcc* z!dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot* z  +! 3{3 :mutex@1400f000mediatek,mt8195-vpp-mutex*P z!3smi@14010000mediatek,mt8195-smi-sub-common*!!!apbsmigals0 E|3}smi@14011000mediatek,mt8195-smi-sub-common*!!!apbsmigals0 E|3smi@14012000mediatek,mt8195-smi-common-vpp*  !!!!apbsmigals0gals13|larb@14013000mediatek,mt8195-smi-larb*0 R E}!!apbsmi3iommu@14018000mediatek,mt8195-iommu-vpp*8 c~R!bclk@3{clock-controller@14e00000mediatek,mt8195-wpesys*&clock-controller@14e02000mediatek,mt8195-wpesys_vpp0* clock-controller@14e03000mediatek,mt8195-wpesys_vpp1*0larb@14e04000mediatek,mt8195-smi-larb*@ R E&&apbsmi3larb@14e05000mediatek,mt8195-smi-larb*P R E|&&! apbsmigals3syscon@14f00000mediatek,mt8195-vppsys1syscon* z %mutex@14f01000mediatek,mt8195-vpp-mutex*{ z %'3larb@14f02000mediatek,mt8195-smi-larb*  R E%%! apbsmigals3larb@14f03000mediatek,mt8195-smi-larb*0 R E}%%! apbsmigals3display@14f06000mediatek,mt8195-mdp3-split*` z `%%+%,3display@14f07000mediatek,mt8195-mdp3-tcc*p z p%dma-controller@14f08000mediatek,mt8195-mdp3-rdma* z  % 33 :dma-controller@14f09000mediatek,mt8195-mdp3-rdma* z  %  33 :dma-controller@14f0a000mediatek,mt8195-mdp3-rdma* z  %  3{3 :display@14f0b000mediatek,mt8195-mdp3-fg* z % display@14f0c000mediatek,mt8195-mdp3-fg* z % display@14f0d000mediatek,mt8195-mdp3-fg* z % display@14f0e000mediatek,mt8195-mdp3-hdr* z %display@14f0f000mediatek,mt8195-mdp3-hdr* z %display@14f10000mediatek,mt8195-mdp3-hdr* z % display@14f11000mediatek,mt8195-mdp3-aal*i z %3display@14f12000mediatek,mt8195-mdp3-aal* j z %3display@14f13000mediatek,mt8195-mdp3-aal*0k z 0%!3display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz*@ z @ %display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz*P z P %$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz*` z ` %%display@14f17000mediatek,mt8195-mdp3-tdshp*p z p%display@14f18000mediatek,mt8195-mdp3-tdshp* z %(display@14f19000mediatek,mt8195-mdp3-tdshp* z %)display@14f1a000mediatek,mt8195-mdp3-merge* z %3display@14f1b000mediatek,mt8195-mdp3-merge* z %3display@14f1c000mediatek,mt8195-mdp3-color*t z %3display@14f1d000mediatek,mt8195-mdp3-color* z u%3display@14f1e000mediatek,mt8195-mdp3-color*v z %3display@14f1f000mediatek,mt8195-mdp3-ovl*w z %3 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E+apbsmi3clock-controller@15330000mediatek,mt8195-ipesys*3,larb@15340000mediatek,mt8195-smi-larb*4 R  E,,apbsmi3clock-controller@16000000mediatek,mt8195-camsys*-larb@16001000mediatek,mt8195-smi-larb* R  E--- apbsmigals3larb@16002000mediatek,mt8195-smi-larb*  R E--apbsmi3smi@16004000mediatek,mt8195-smi-sub-common*@---apbsmigals0 E3smi@16005000mediatek,mt8195-smi-sub-common*P--!apbsmigals0 E|3larb@16012000mediatek,mt8195-smi-larb*  R Eapbsmi3 larb@16013000mediatek,mt8195-smi-larb*0 R Eapbsmi3 larb@16014000mediatek,mt8195-smi-larb*@ R Eapbsmi3!larb@16015000mediatek,mt8195-smi-larb*P R Eapbsmi3!clock-controller@1604f000mediatek,mt8195-camsys_rawa*clock-controller@1606f000mediatek,mt8195-camsys_yuva*clock-controller@1608f000mediatek,mt8195-camsys_rawb*clock-controller@160af000mediatek,mt8195-camsys_yuvb* clock-controller@16140000mediatek,mt8195-camsys_mraw*larb@16141000mediatek,mt8195-smi-larb* R E-- apbsmigals3"larb@16142000mediatek,mt8195-smi-larb*  R Eapbsmi3"clock-controller@17200000mediatek,mt8195-ccusys* larb@17201000mediatek,mt8195-smi-larb*  R Eapbsmi3video-codec@18000000mediatek,mt8195-vcodec-dec r 3+ *@`video-codec@2000mediatek,mtk-vcodec-lat-soc*  3{{ A''selvdeclattop-A=3video-codec@10000mediatek,mtk-vcodec-lat*0 3 A''selvdeclattop-A=3video-codec@25000mediatek,mtk-vcodec-core*PP 3 A""selvdeclattop-A=3larb@1800d000mediatek,mt8195-smi-larb* R E''apbsmi3larb@1800e000mediatek,mt8195-smi-larb* R E!'apbsmi3clock-controller@1800f000mediatek,mt8195-vdecsys_soc*'larb@1802e000mediatek,mt8195-smi-larb* R E""apbsmi3clock-controller@1802f000mediatek,mt8195-vdecsys*"larb@1803e000mediatek,mt8195-smi-larb* R E!(apbsmi3clock-controller@1803f000mediatek,mt8195-vdecsys_core1*(clock-controller@190f3000mediatek,mt8195-apusys_pll*0clock-controller@1a000000mediatek,mt8195-vencsys*)larb@1a010000mediatek,mt8195-smi-larb* R E))apbsmi3video-codec@1a020000mediatek,mt8195-vcodec-enc*H 3`abcdvwxyU r) venc_sel-@=3+jpgdec-mastermediatek,mt8195-jpgdec30 3mnrstu+jpgdec@1a040000mediatek,mt8195-jpgdec-hw*0 3mnrstuW)jpgdec3jpgdec@1a050000mediatek,mt8195-jpgdec-hw*0 3mnrstuX)jpgdec3jpgdec@1b040000mediatek,mt8195-jpgdec-hw*0 3{{{{{{\#jpgdec3clock-controller@1b000000mediatek,mt8195-vencsys_core1*#syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon*  $jpgenc-mastermediatek,mt8195-jpgenc3 3{{{{+jpgenc@1a030000mediatek,mt8195-jpgenc-hw* 3ghilV)jpgenc3jpgenc@1b030000mediatek,mt8195-jpgenc-hw* 3{{{{[#jpgenc3larb@1b010000mediatek,mt8195-smi-larb* R E|##!  apbsmigals3ovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl*|3$ 3 rdma@1c002000mediatek,mt8195-disp-rdma* ~3$ 3  color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color*03$ 0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr*@3$ @aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal*P3$ Pgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma*`3$ `dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither*p3$  pdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi*3$$*enginedigitalhs { dphy disableddsc@1c009000mediatek,mt8195-disp-dsc*3$ dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi* 3$$+enginedigitalhs { dphy disabledmerge@1c014000mediatek,mt8195-disp-merge*@3$ @dp-intf@1c015000mediatek,mt8195-dp-intf*P$$,enginepixelpllokayportendpoint mutex@1c016000mediatek,mt8195-disp-mutex*`3$ ` Ularb@1c018000mediatek,mt8195-smi-larb* R E$($(!  apbsmigals3larb@1c019000mediatek,mt8195-smi-larb* R E|$(! ! apbsmigals3~syscon@1c100000mediatek,mt8195-vdosys1syscon*  *smi@1c01b000mediatek,mt8195-smi-common-vdo* $%$&$)$$apbsmigals0gals13iommu@1c01f000mediatek,mt8195-iommu-vdo*8 c@$'bclk3mutex@1c101000mediatek,mt8195-disp-mutex*  vdo1_mutex3* vdo1_mutex  larb@1c102000mediatek,mt8195-smi-larb*  R E*** apbsmigals3larb@1c103000mediatek,mt8195-smi-larb*0 R E|**!  apbsmigals3dma-controller@1c104000mediatek,mt8195-vdo1-rdma*@*3 3@ @ :dma-controller@1c105000mediatek,mt8195-vdo1-rdma*P*3 3{` P :dma-controller@1c106000mediatek,mt8195-vdo1-rdma*`*3 3A ` :dma-controller@1c107000mediatek,mt8195-vdo1-rdma*p*3 3{a p :dma-controller@1c108000mediatek,mt8195-vdo1-rdma**3 3B  :dma-controller@1c109000mediatek,mt8195-vdo1-rdma**3 3{b  :dma-controller@1c10a000mediatek,mt8195-vdo1-rdma**3 3C  :dma-controller@1c10b000mediatek,mt8195-vdo1-rdma**3 3{c  :vpp-merge@1c10c000mediatek,mt8195-disp-merge** *mergemerge_async3  *vpp-merge@1c10d000mediatek,mt8195-disp-merge** *mergemerge_async3  *vpp-merge@1c10e000mediatek,mt8195-disp-merge** *mergemerge_async3  *vpp-merge@1c10f000mediatek,mt8195-disp-merge** *mergemerge_async3  *vpp-merge@1c110000mediatek,mt8195-disp-merge** *mergemerge_async3  *dp-intf@1c113000mediatek,mt8195-dp-intf*03**/enginepixelpllokayportendpoint hdr-engine@1c114000mediatek,mt8195-disp-ethdrp*@Pp4 mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Pph*%* *#*!*$*"*1*&*'*(*)**mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top3 3{d{e(*3*4*5*6*7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-tx*Pdp_calibration_data3 okaydefaultports+port@0*endpoint port@1*endpoint  aux-buspanel edp-panel  portendpoint dp-tx@1c600000mediatek,mt8195-dp-tx*`dp_calibration_data3 okaydefaultports+port@0*endpoint port@1*endpoint thermal-zonescpu0-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcooling-mapsmap0 80 = cpu1-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcooling-mapsmap0 80 = cpu2-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcooling-mapsmap0 80 = cpu3-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcooling-mapsmap0 80 = cpu4-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcooling-mapsmap0 80 =cpu5-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcooling-mapsmap0 80 =cpu6-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcooling-mapsmap0 80 =cpu7-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcooling-mapsmap0 80 =vpu0-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalvpu1-thermal    tripstrip-alert !L -%passivetrip-crit ! - %criticalgpu0-thermal    tripstrip-alert !L -%passivetrip-crit ! - %criticalgpu1-thermal    tripstrip-alert !L -%passivetrip-crit ! - %criticalvdec-thermal    tripstrip-alert !L -%passivetrip-crit ! - %criticalimg-thermal    tripstrip-alert !L -%passivetrip-crit ! - %criticalinfra-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcam0-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalcam1-thermal   tripstrip-alert !L -%passivetrip-crit ! - %criticalsoc-area-thermal   tripstrip-crit !H  - %criticalpmic-area-thermal   tripstrip-crit !H  - %criticalbacklight-lcd0pwm-backlight L ^@ wR    chosen serial0:115200n8memory@40000000memory*@regulator-pp3300-disp-xregulator-fixedpp3300_disp_x2Z2Z   7default eregulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5 2Z2Z fregulator-pp3300-s3regulator-fixed pp3300_s3 2Z2Z ebregulator-pp3300-z2regulator-fixed pp3300_z2 2Z2Z eregulator-pp4200-z2regulator-fixed pp4200_z2 @@@@ regulator-pp5000-s5regulator-fixed pp5000_s5 LK@LK@ regulator-ppvar-sysregulator-fixed ppvar_sys thermal-sensor-t1generic-adc-thermal"  sensor-channel x~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,thermal-sensor-t2generic-adc-thermal"  sensor-channel x~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,regulator-5v0-usb-vbusregulator-fixed usb-vbusLK@LK@ Greserved-memory+memory@50000000shared-dma-pool*P0memory@60000000shared-dma-pool*`7memory@60d80000shared-dma-pool*`9memory@60e80000shared-dma-pool*`(6rt1019prealtek,rt1019prt1019pdefault $d compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platformmediatek,adspmediatek,dai-linkpinctrl-namespinctrl-0#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitgpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgassigned-clocksassigned-clock-parentsinterrupts-extendedmediatek,dmic-modemediatek,mic-type-0regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namesmediatek,etdm-in2-cowork-sourcemediatek,etdm-out2-cowork-source#io-channel-cellsmediatek,pad-selectspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupwakeup-sourcerx-fifo-depthvusb33-supplyvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104usb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsi2c-scl-internal-delay-nsvcc-supplyrealtek,jd-srcAVDD-supplyMICVDD-supplyVBAT-supplyrealtek,amic-delay-mshid-descr-addrpost-power-on-delay-msvdd-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsmediatek,scpremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanespower-supplybacklightpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicebrightness-levelsdefault-brightness-levelenable-gpiosnum-interpolated-stepspwmsstdout-pathenable-active-highgpiovin-supplyregulator-boot-onio-channelsio-channel-namestemperature-lookup-tableno-maplabelsdb-gpios