p@8id(i,sony,xperia-m5mediatek,mt6795 +7Sony Xperia M5=handsetaliasesJ/soc/ovl@1400c000O/soc/ovl@1400d000T/soc/rdma@1400e000Z/soc/rdma@1400f000`/soc/rdma@14010000f/soc/wdma@14011000l/soc/wdma@14012000r/soc/color@14013000y/soc/color@14014000/soc/split@14018000/soc/split@14019000/soc/dpi@1401d000/soc/dsi@1401b000/soc/dsi@1401c000/soc/mmc@11230000/soc/mmc@11240000/soc/mmc@11250000/soc/serial@11002000/soc/serial@11003000psci arm,psci-0.2smccpus+cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53psci @*7D@Vcpu@2cpuarm,cortex-a53psci @*7D@Vcpu@3cpuarm,cortex-a53psci @*7D@V cpu@100cpuarm,cortex-a53psci @*7D@V cpu@101cpuarm,cortex-a53psci @*7D@V cpu@102cpuarm,cortex-a53psci @*7D@V cpu@103cpuarm,cortex-a53psci @*7D@V cpu-mapcluster0core0ccore1ccore2ccore3c cluster1core0c core1c core2c core3c l2-cache0cacheg @,sl2-cache1cacheg @,soscillator-26m fixed-clockclk26moscillator-32k fixed-clock}clk32kdummy13m fixed-clock]@pmuarm,cortex-a53-pmu0    timerarm,armv8-timer 0   soc+ simple-bussyscon@10000000 mediatek,mt6795-topckgensysconsyscon@10001000 mediatek,mt6795-infracfgsysconsyscon@10003000mediatek,mt6795-pericfgsyscon0syscon@10006000sysconsimple-mfd`power-controller!mediatek,mt6795-power-controller+power-domain@1Rmmpower-domain@2RUmmvencpower-domain@3Rmmpower-domain@0Rmm power-domain@4Remmmjcpower-domain@5power-domain@6mfg+power-domain@7+power-domain@8 pinctrl@10005000mediatek,mt6795-pinctrl P baseeint&6BNclcm-pins6pins-rsttjemmc-sdr-pins'pins-cmd-dat$t{epins-clktfpins-rsttfemmc-uhs-pins(pins-cmd-dat$t{epins-clktfpins-rsttfpins-dstfnfc-pins%pins-irqt{pins-fw-vent^touchscreen-pins#pins-irqt{pins-rsttfproximity-pins&pins-irqt{accelerometer-pins!pins-irqt {i2c0-pinspins-bust-.{i2c1-pins pins-bust}~i2c2-pins"pins-bust+,i2c3-pins$pins-busti2c4-pinspins-bustdeuart0-pinspins-rxtq{pins-txtruart2-pinspins-rxt{pins-txt watchdog@10007000mediatek,mt6795-wdtp timer@10008000,mediatek,mt6795-timermediatek,mt6577-timer pwrap@1000d000mediatek,mt6795-pwrappwrap pwrap c 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/syscon@10209000"mediatek,mt6795-apmixedsyssyscon clock-controller@10209f00mediatek,mt6795-fhctl okay mailbox@10212000(mediatek,mt6795-gcemediatek,mt8173-gce!  gce -dsi-phy@10215000mediatek,mt8173-mipi-tx!P mipi_tx0_pll disabled0dsi-phy@10216000mediatek,mt8173-mipi-tx!` mipi_tx1_pll disabled9interrupt-controller@10221000 arm,gic-400c N@"" "@ "`   cci@10390000 arm,cci-400+99slave-if@1000arm,cci-400-ctrl-if !ace-liteslave-if@4000arm,cci-400-ctrl-if!ace@slave-if@5000arm,cci-400-ctrl-if!acePpmu@9000arm,cci-400-pmu,r1P<:;<=>serial@11002000*mediatek,mt6795-uartmediatek,mt6577-uart  [ baudbus05txrxokay?defaultMserial@11003000*mediatek,mt6795-uartmediatek,mt6577-uart0 \ baudbus05txrx disableddma-controller@110003802mediatek,mt6795-uart-dmamediatek,mt6577-uart-dma`````````ghijklmnW apdmadxserial@11004000*mediatek,mt6795-uartmediatek,mt6577-uart@ ]  baudbus05txrxokay?defaultMserial@11005000*mediatek,mt6795-uartmediatek,mt6577-uartP ^! baudbus05txrx disabledpwm@11006000mediatek,mt6795-pwm` MHS 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.-dsi@1401b000(mediatek,mt6795-dsimediatek,mt8173-dsi .$.%0enginedigitalhs0dphyokay+panel@0sharp,ls060t1sx01123'4 3j?5M6?defaultportendpointI78portendpointI87dsi@1401c000(mediatek,mt6795-dsimediatek,mt8173-dsi .&.'9enginedigitalhs9dphy disableddpi@1401d000(mediatek,mt6795-dpimediatek,mt8183-dpi .(.)pixelenginepll disabledpwm@1401e0002mediatek,mt6795-disp-pwmmediatek,mt8173-disp-pwm.!. mainmmokay?pwm@1401f0002mediatek,mt6795-disp-pwmmediatek,mt8173-disp-pwm.#."mainmm disabledmutex@14020000mediatek,mt8173-disp-mutex .Y45-larb@14021000mediatek,mt6795-smi-larb..apbsmim:zsmi@14022000mediatek,mt6795-smi-common .apbsmi:od@140230000mediatek,mt6795-disp-odmediatek,mt8173-disp-od0.-0larb@15001000mediatek,mt6795-smi-larb.apbsmim:zclock-controller@16000000mediatek,mt6795-vdecsys;larb@16010000mediatek,mt6795-smi-larbm:z;;apbsmiclock-controller@18000000mediatek,mt6795-vencsys<larb@18001000mediatek,mt6795-smi-larb<<apbsmim:zbacklightled-backlight=>,5led-controller-display pwm-ledsled-0backlight-pwm ? =memory@40000000memory@reserved-memory+secmon@43000000Cpreloader-region@44800000Dbootloader-region@46000000F@regulator-disp-avddregulator-fixed disp_avddLK@LK@ 1regulator-disp-aveeregulator-fixed disp_aveeLK@LK@ 2regulator-disp-vddhregulator-fixed disp_vddhw@w@s4 compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mmc0mmc1mmc2serial0serial1methoddevice_typeenable-methodregcci-control-portnext-level-cachephandlei-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setscpucache-levelcache-unified#clock-cellsclock-frequencyclock-output-namesinterruptsinterrupt-affinityranges#reset-cells#power-domain-cellsclocksclock-namesmediatek,infracfgreg-namesgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspinmuxinput-enablebias-pull-upbias-pull-downdrive-strengthoutput-highbias-disabletimeout-secresetsreset-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-allowed-modesregulator-always-onregulator-boot-onlinux,keycodeswakeup-sourcelabelmediatek,larbspower-domains#iommu-cellsstatusmediatek,hopping-ssc-percent#mbox-cells#phy-cellsinterface-typedmasdma-namespinctrl-namespinctrl-0dma-requestsmediatek,dma-33bits#dma-cells#pwm-cellsclock-divinterrupts-extendedsyna,startup-delay-mssyna,reset-delay-mssyna,nosleep-modesyna,sensor-typeenable-gpiosfirmware-gpiosmediatek,latch-ckmediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-ds-dly3non-removablepinctrl-1vmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-ratesmboxesmediatek,gce-client-regiommusphysphy-namesavdd-supplyavee-supplyvddi-supplyvddh-supplyreset-gpiosbacklightremote-endpointmediatek,gce-eventsmediatek,smimediatek,larb-idledsdefault-brightness-levelpwmsmax-brightnessno-mapgpioenable-active-high