8( ,Freescale i.MX8DXL EVK2fsl,imx8dxl-evkfsl,imx8dxlaliases =/bus@5b000000/ethernet@5b040000 G/bus@5b000000/ethernet@5b050000Q/bus@5d000000/gpio@5d080000W/bus@5d000000/gpio@5d090000]/bus@5d000000/gpio@5d0a0000c/bus@5d000000/gpio@5d0b0000i/bus@5d000000/gpio@5d0c0000o/bus@5d000000/gpio@5d0d0000u/bus@5d000000/gpio@5d0e0000{/bus@5d000000/gpio@5d0f0000/bus@5d000000/mailbox@5d1c0000/bus@5a000000/i2c@5a820000/bus@5b000000/mmc@5b010000/bus@5b000000/mmc@5b020000/bus@5a000000/serial@5a060000cpus cpu@0cpu2arm,cortex-a35psci  cpu@1cpu2arm,cortex-a35psci  l2-cache02cache opp-table2operating-points-v2opp-900000000"5)B@7Iopp-1200000000"G)7IHinterrupt-controller@51a00000 2arm,gic-v3 QQ Te z reserved-memory dsp@92400000@linux,cma2shared-dma-poolpmu2arm,armv8-pmuv3 zpsci 2arm,psci-1.0smcsystem-controller 2fsl,imx-scu tx0rx0gip3$power-controller 2fsl,scu-pd8 clock-controller2fsl,imx8dxl-clkfsl,scu-clkgpio2fsl,imx8qxp-sc-gpioQpinctrl2fsl,imx8dxl-iomuxcdefault(Khoggrp02<I@LkLusbotg1grp 2!*usbotg2grp 2!Feqosgrp2- , 3 9 6 5 4 : / 7 8 0 2 1 :flexspi0grp2y!x!{!z!}!|!~!!!!!!!!Lfec1grp2#*- , $`&`'`(`)`%``` `!`"``5lpspi3grp02=@>@?@A@i2c2grp2s!t!!cm40lpuartgrp2S R i2c3grp2v!u!lpuart0grp2\ ] usdhc1grp2 A ! ! ! !!!!!!A-usdhc2gpiogrp$2@ !!!0usdhc2grpT2$A%!&!'!(!)!!/ocotp2fsl,imx8qxp-scu-ocotp mac@2c47mac@2c6<rtc2fsl,imx8qxp-sc-rtckeys"2fsl,imx8qxp-sc-keyfsl,imx-sc-key;tJwatchdog2fsl,imx-sc-wdtX<thermal-sensor2fsl,imx-sc-thermaldtimer2arm,armv8-timer0z   thermal-zonescpu-thermalzctripstrip0passivetrip1 criticalcooling-mapsmap0 pmic-thermalztripstrip0passive trip1H criticalcooling-mapsmap0  clock-xtal32k 2fixed-clock xtal_32KHzclock-xtal24m 2fixed-clockn6 xtal_24MHzbus@59000000 2simple-bus YYclock-audio-ipg 2fixed-clock haudio_ipg_clk clock-controller@595800002fsl,imx8qxp-lpcgYX  4dsp_lpcg_adb_clkdsp_lpcg_ipg_clkdsp_lpcg_core_clk clock-controller@595900002fsl,imx8qxp-lpcgYY dsp_ram_lpcg_ipg_clk dsp@596e80002fsl,imx8qxp-dspYnipgocramcore   txdb0txdb1rxdb0rxdb10$ 2disabledbus@5a000000 2simple-bus ZZclock-dma-ipg 2fixed-clock h dma_ipg_clkspi@5a0000002fsl,imx7ulp-spiZ  zperipg 95I 5 2disabledspi@5a0100002fsl,imx7ulp-spiZ  zperipg 96I 6 2disabledspi@5a0200002fsl,imx7ulp-spiZ  zperipg 97I 7 2disabledspi@5a0300002fsl,imx7ulp-spiZ  zperipg 98I 82okay^default( wspi@02rohm,dh2228fvÀserial@5a060000Z z ipgbaud 99IĴ 92okay&2fsl,imx8dxl-lpuartfsl,imx8qxp-lpuartdefault(serial@5a070000Z z ipgbaud 9:IĴ : 2disabled&2fsl,imx8dxl-lpuartfsl,imx8qxp-lpuartserial@5a080000Z z ipgbaud 9;IĴ ; 2disabled&2fsl,imx8dxl-lpuartfsl,imx8qxp-lpuartserial@5a090000Z  z ipgbaud 9<IĴ < 2disabled&2fsl,imx8dxl-lpuartfsl,imx8qxp-lpuartclock-controller@5a4000002fsl,imx8qxp-lpcgZ@5 spi0_lpcg_clkspi0_lpcg_ipg_clk 5clock-controller@5a4100002fsl,imx8qxp-lpcgZA6 spi1_lpcg_clkspi1_lpcg_ipg_clk 6clock-controller@5a4200002fsl,imx8qxp-lpcgZB7 spi2_lpcg_clkspi2_lpcg_ipg_clk 7clock-controller@5a4300002fsl,imx8qxp-lpcgZC8 spi3_lpcg_clkspi3_lpcg_ipg_clk 8clock-controller@5a4600002fsl,imx8qxp-lpcgZF9'uart0_lpcg_baud_clkuart0_lpcg_ipg_clk 9clock-controller@5a4700002fsl,imx8qxp-lpcgZG:'uart1_lpcg_baud_clkuart1_lpcg_ipg_clk :clock-controller@5a4800002fsl,imx8qxp-lpcgZH;'uart2_lpcg_baud_clkuart2_lpcg_ipg_clk ;clock-controller@5a4900002fsl,imx8qxp-lpcgZI<'uart3_lpcg_baud_clkuart3_lpcg_ipg_clk <i2c@5a800000Z@ zperipg 9`In6 ` 2disabled62fsl,imx8dxl-lpi2cfsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000Z@ zperipg 9aIn6 a 2disabled62fsl,imx8dxl-lpi2cfsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a820000Z@ z peripg 9bIn6 b2okay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c default(!gpio@20 2ti,tca6416 gpio@21 2ti,tca6416!Ni2c-mux@70 2nxp,pca9548 pi2c@0 gpio@682maxim,max7322h 2disabledOi2c@4 i2c@5 i2c@6 i2c@5a830000Z@ z""peripg 9cIn6 c 2disabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2cadc@5a8800002nxp,imx8qxp-adcZ z##peripg 9eIn6 e2okay$adc@5a8900002nxp,imx8qxp-adcZ z%%peripg 9fIn6 f 2disabledcan@5a8d00002fsl,imx8qm-flexcanZ z&&ipgper 9iIbZ i 2disabledcan@5a8e00002fsl,imx8qm-flexcanZ z&&ipgper 9iIbZ j 2disabledcan@5a8f00002fsl,imx8qm-flexcanZ z&&ipgper 9iIbZ k 2disabledclock-controller@5ac000002fsl,imx8qxp-lpcgZ` i2c0_lpcg_clki2c0_lpcg_ipg_clk `clock-controller@5ac100002fsl,imx8qxp-lpcgZa i2c1_lpcg_clki2c1_lpcg_ipg_clk aclock-controller@5ac200002fsl,imx8qxp-lpcgZb i2c2_lpcg_clki2c2_lpcg_ipg_clk b clock-controller@5ac300002fsl,imx8qxp-lpcgZc i2c3_lpcg_clki2c3_lpcg_ipg_clk c"clock-controller@5ac800002fsl,imx8qxp-lpcgZe adc0_lpcg_clkadc0_lpcg_ipg_clk e#clock-controller@5ac900002fsl,imx8qxp-lpcgZf adc1_lpcg_clkadc1_lpcg_ipg_clk f%clock-controller@5acd00002fsl,imx8qxp-lpcgZi 5can0_lpcg_pe_clkcan0_lpcg_ipg_clkcan0_lpcg_chi_clk i&bus@5b000000 2simple-bus [[clock-conn-axi 2fixed-clockCU conn_axi_clkAclock-conn-ahb 2fixed-clock ! conn_ahb_clkCclock-conn-ipg 2fixed-clock conn_ipg_clk@usb@5b0d0000-2fsl,imx7ulp-usbfsl,imx6ul-usbfsl,imx27-usb[  z'() 2okaydefault(*)5AM_usbmisc@5b0d0200t82fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc[ (usbphy@5b1000002fsl,imx7ulp-usbphy[+ 2okayr'mmc@5b010000 z[,,, ipgahbper 2okay$2fsl,imx8dxl-usdhcfsl,imx8qxp-usdhcdefault(-mmc@5b020000 z[... ipgahbper 2okay$2fsl,imx8dxl-usdhcfsl,imx8qxp-usdhcdefault(/01 2 2mmc@5b030000 z[333 ipgahbper  2disabled$2fsl,imx8dxl-usdhcfsl,imx8qxp-usdhcethernet@5b040000[0z 444 4ipgahbenet_clk_refptp 9IsY@   2disabled2fsl,imx8qm-fecdefault(5 rgmii-txid$6/@U7 amac-addressmdio ethernet-phy@12ethernet-phy-ieee802.3-c22 r~'86vddio-regulatorw@w@8ethernet@5b050000[z(99999stmmacethpclkptp_reftxmem 9IsY@ 2okay(2nxp,imx8dxl-dwmac-eqossnps,dwmac-5.10aeth_wake_irqmacirqdefault(: rgmii-id$;U< amac-addressmdio2snps,dwmac-mdio ethernet-phy@02ethernet-phy-ieee802.3-c22 r~ @=;vddio-regulatorw@w@=usb@5b1100002fsl,imx8qm-usb3[ (>>>>>lpmbusaclkipgcore 9I沀  2disabledusb@5b120000 2cdns,usb3[[[ 0otgxhcidev0zhostperipheralotgwakeup:??cdns3,usb3-phyI 2disabledusb-phy@5b1600002nxp,salvo-phy[>salvo_phy_clk ` 2disabled?clock-controller@5b2000002fsl,imx8qxp-lpcg[ @A 9sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clk ,clock-controller@5b2100002fsl,imx8qxp-lpcg[!@A 9sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clk .clock-controller@5b2200002fsl,imx8qxp-lpcg["@A 9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clk 3clock-controller@5b2300002fsl,imx8qxp-lpcg[# BBA@@ enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clk 4clock-controller@5b2400002fsl,imx8qxp-lpcg[$BAA@6eqos_ptpeqos_mem_clkeqos_aclkeqos_clkeqos_csr_clk 9clock-controller@5b2700002fsl,imx8qxp-lpcg['C@"usboh3_ahb_clkusboh3_phy_ipg_clk +clock-controller@5b2800002fsl,imx8qxp-lpcg[(@usboh3_2_phy_ipg_clk >clock-conn-enet0-root 2fixed-clock沀conn_enet0_root_clkBusb@5b0e0000/2fsl,imx8dxl-usbfsl,imx7ulp-usbfsl,imx6ul-usb[ zDE) 2okaydefault(F)5AM_clock-dummy 2fixed-clock clk_dummy)usbmisc@5b0e0200t82fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc[Eusbphy@5b110000&2fsl,imx8dxl-usbphyfsl,imx7ulp-usbphy[> 2okayoDbus@5c000000 2simple-bus \\ddr-pmu@5c0200002fsl,imx8-ddr-pmu\ zGbus@5d000000 2simple-bus  ]]clock-lsio-mem 2fixed-clock  lsio_mem_clkclock-lsio-bus 2fixed-clock lsio_bus_clkMpwm@5d0000002fsl,imx27-pwm]ipgperGG 9In6k z^ 2disabledpwm@5d0100002fsl,imx27-pwm]ipgperHH 9In6k z_ 2disabledpwm@5d0200002fsl,imx27-pwm]ipgperII 9In6k z` 2disabledpwm@5d0300002fsl,imx27-pwm]ipgperJJ 9In6k za 2disabledgpio@5d080000] zNeT  2fsl,imx8dxl-gpiofsl,imx35-gpio@vK/ K =KCKHgpio@5d090000]  zOeT  2fsl,imx8dxl-gpiofsl,imx35-gpio vKJK Pgpio@5d0a0000]  zPeT  2fsl,imx8dxl-gpiofsl,imx35-gpio0vKbKeKkgpio@5d0b0000]  zQeT  2fsl,imx8dxl-gpiofsl,imx35-gpiovKsK yK xK {K zK }K|K~KKKKKKKgpio@5d0c0000]  zReT  2fsl,imx8dxl-gpiofsl,imx35-gpio`vKKK KKK2okayPgpio@5d0d0000]  zSeT  2fsl,imx8dxl-gpiofsl,imx35-gpio0vK K$K +2okay2gpio@5d0e0000] zTeT  2fsl,imx8dxl-gpiofsl,imx35-gpio0vK5KV Kkgpio@5d0f0000] zUeT  2fsl,imx8dxl-gpiofsl,imx35-gpioPvKKKK K,spi@5d120000 2nxp,imx8dxl-fspi]0fspi_basefspi_mmap z" fspi_enfspi 2okaydefault(Lflash@0 2jedec,spi-nork@mailbox@5d1b0000] zV 2disabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1c0000] zW-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1d0000] zX 2disabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1e0000] zY 2disabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1f0000] zZ 2disabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d200000]  z[  2disabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d210000]! z  2disabledmailbox@5d280000]( z clock-controller@5d4000002fsl,imx8qxp-lpcg]@4Mhpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clk Gclock-controller@5d4100002fsl,imx8qxp-lpcg]A4Mhpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clk Hclock-controller@5d4200002fsl,imx8qxp-lpcg]B4Mhpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clk Iclock-controller@5d4300002fsl,imx8qxp-lpcg]C4Mhpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clk Jclock-controller@5d4400002fsl,imx8qxp-lpcg]D4Mhpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clk clock-controller@5d4500002fsl,imx8qxp-lpcg]E4Mhpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clk clock-controller@5d4600002fsl,imx8qxp-lpcg]F4Mhpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clk clock-controller@5d4700002fsl,imx8qxp-lpcg]G4Mhpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clk chosen/bus@5a000000/serial@5a060000memory@80000000memory@regulator-02regulator-fixed2Z2Zmux3_en Nregulator-12regulator-fixed fec1_supply2Z2Z   2disabledregulator-22regulator-fixedfec1_io_supplyw@w@ O 2disabledregulator-32regulator-fixed SD1_SPWR-- P 1regulator-adc-vref2regulator-fixed vref_1v8w@w@$regulator-42regulator-fixed mii-select2Z2Z Q interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0ethernet1gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7mu1i2c2mmc0mmc1serial0device_typeregenable-methodnext-level-cacheclocks#cooling-cellsoperating-points-v2phandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsrangesno-mapreusablesizealloc-rangeslinux,cma-defaultmbox-namesmboxes#power-domain-cellswakeup-irq#clock-cellsgpio-controller#gpio-cellspinctrl-namespinctrl-0fsl,pinslinux,keycodeswakeup-sourcetimeout-sec#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceclock-frequencyclock-output-namesclock-indicespower-domainsclock-namesmemory-regionstatusassigned-clocksassigned-clock-ratesfsl,spi-only-use-cs1-selpinctrl-assert-gpiosspi-max-frequency#io-channel-cellsvref-supplyfsl,clk-sourcefsl,scu-indexfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dwordsrp-disablehnp-disableadp-disablepower-active-highdisable-over-current#index-cellsfsl,tx-d-calbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetrx-internal-delay-psnvmem-cellsnvmem-cell-namesreset-gpiosreset-assert-usqca,disable-smarteeevddio-supplyregulator-min-microvoltregulator-max-microvoltinterrupt-nameseee-broken-1000tqca,disable-hibernation-modereset-deassert-usreg-namesphysphy-namescdns,on-chip-buff-size#phy-cells#pwm-cellsgpio-rangesnxp,fspi-dll-slvdlyspi-tx-bus-widthspi-rx-bus-width#mbox-cellsstdout-pathregulator-namegpioregulator-always-onenable-active-highoff-on-delay-us