[8V(V!,rikomagic,mk808rockchip,rk3066a7Rikomagic MK808aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000/spi@20070000/spi@20074000/mmc@10214000/mmc@10218000oscillator ,fixed-clockn6xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400  buscorex disabledx5gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3)video-codec@10104000,rockchip,rk3066-vpu@   vepuvdpu (aclk_vdpuhclk_vdpuaclk_vepuhclk_vepu)cache-controller@10138000,arm,pl310-cache7EQ/scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer   local-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicYnQserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@ "baudclkapb_pclk@L disabledtxrxdefaultserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart` #baudclkapb_pclkAM disabledtxrxdefaultqos@1012d000,rockchip,rk3066-qossyscon Qqos@1012e000,rockchip,rk3066-qossyscon Qqos@1012f000,rockchip,rk3066-qossyscon Qqos@1012f080,rockchip,rk3066-qossyscon Qqos@1012f100,rockchip,rk3066-qossyscon Qqos@1012f180,rockchip,rk3066-qossyscon Qqos@1012f200,rockchip,rk3066-qossyscon Qqos@1012f280,rockchip,rk3066-qossyscon Qusb@10180000,rockchip,rk3066-usbsnps,dwc2 otgotg@@  usb2-phyokayusb@101c0000 ,snps,dwc2 otghost usb2-phyokayethernet@10204000,rockchip,rk3066-emac @<  D hclkmacrefdrmii disabledmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciu rx-tx$Q/resetokay;default ISevmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciu rx-tx$R/resetokaydefault Ivmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciu rx-tx$S/reset disablednand-controller@10500000,rockchip,rk2928-nfcP@ ahb disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode@RBRBRB RBpower-controller!,rockchip,rk3066-power-controllerQpower-domain@7POpower-domain@6 power-domain@8grf@20008000&,rockchip,rk3066-grfsysconsimple-mfd Q usbphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyokayusb-phy@17c|QphyclkQusb-phy@188RphyclkQdma-controller@20018000,arm,pl330arm,primecell @ apb_pclkQdma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk disabledi2c@2002d000,rockchip,rk3066-i2c  ( i2cP disableddefaulti2c@2002f000,rockchip,rk3066-i2c  ) Qi2c disableddefaultpwm@20030000,rockchip,rk2928-pwm 0F disableddefaultpwm@20030010,rockchip,rk2928-pwm 0F disableddefaultwatchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3okaypwm@20050020,rockchip,rk2928-pwm  0G disableddefault pwm@20050030,rockchip,rk2928-pwm 00G disableddefault!i2c@20056000,rockchip,rk3066-i2c ` * Ri2c disableddefault"i2c@2005a000,rockchip,rk3066-i2c  + Si2c disableddefault#i2c@2005e000,rockchip,rk3066-i2c  4 Ti2c disableddefault$serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @ $baudclkapb_pclkBNokay  txrxdefault%serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart  %baudclkapb_pclkCO disabled  txrxdefault&saradc@2006c000,rockchip,saradc  ;GJsaradcapb_pclkW /saradc-apb disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk &  txrx disableddefault'()*spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @ txrx disableddefault+,-.dma-controller@20078000,arm,pl330arm,primecell @ apb_pclkQ cpusMrockchip,rk3066-smpcpu@0[cpu,arm,cortex-a9g/8x@ Oa* s* 'g8@cpu@1[cpu,arm,cortex-a9g/display-subsystem,rockchip,display-subsystem01sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3066-vop  aclk_vopdclk_vophclk_vop)def /axiahbdclkokayportQ0endpoint@02Q6vop@1010e000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop)ghi /axiahbdclk disabledportQ1endpoint@03Q7hdmi@10116000,rockchip,rk3066-hdmi`  @hclkdefault45) okayportsport@0endpoint@06Q2endpoint@17 disabledQ3port@1endpoint8Q?i2s@10118000,rockchip,rk3066-i2s  default9Ki2s_clki2s_hclktxrx disabledi2s@1011a000,rockchip,rk3066-i2s   default:Li2s_clki2s_hclktxrx disabledi2s@1011c000,rockchip,rk3066-i2s  default;Mi2s_clki2s_hclk  txrx disabledclock-controller@20000000,rockchip,rk3066a-cru  @^_ ׄ#gрxhрxhQtimer@2000e000,snps,dw-apb-timer  .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer  ,TB timerpclktimer@2003a000,snps,dw-apb-timer  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk ;\ /saradc-apb disabledpinctrl,rockchip,rk3066a-pinctrl gpio0@20034000,rockchip,gpio-bank @ 6UYnQ>gpio1@2003c000,rockchip,gpio-bank  7VYngpio2@2003e000,rockchip,gpio-bank  8WYngpio3@20080000,rockchip,gpio-bank  9XYnQCgpio4@20084000,rockchip,gpio-bank @ :YYngpio6@2000a000,rockchip,gpio-bank  <ZYnpcfg-pull-default#Q=pcfg-pull-none9Q<emacemac-xferF<<<<<<<<emac-mdio F<<emmcemmc-clkF=emmc-cmdF =emmc-rstF =hdmihdmi-hpdF=Q5hdmii2c-xfer F<<Q4i2c0i2c0-xfer F<<Qi2c1i2c1-xfer F<<Qi2c2i2c2-xfer F<<Q"i2c3i2c3-xfer F<<Q#i2c4i2c4-xfer F<<Q$pwm0pwm0-outF<Qpwm1pwm1-outF<Qpwm2pwm2-outF<Q pwm3pwm3-outF<Q!spi0spi0-clkF=Q'spi0-cs0F=Q*spi0-txF=Q(spi0-rxF=Q)spi0-cs1F=spi1spi1-clkF=Q+spi1-cs0F=Q.spi1-rxF=Q-spi1-txF=Q,spi1-cs1F=uart0uart0-xfer F==Quart0-ctsF=uart0-rtsF=uart1uart1-xfer F==Quart1-ctsF=uart1-rtsF=uart2uart2-xfer F= =Q%uart3uart3-xfer F==Q&uart3-ctsF=uart3-rtsF=sd0sd0-clkF=Q sd0-cmdF =Q sd0-cdF=Q sd0-wpF=sd0-bus-width1F =sd0-bus-width4@F = = = =Qsd1sd1-clkF=Qsd1-cmdF=Qsd1-cdF=sd1-wpF=sd1-bus-width1F=sd1-bus-width4@F====Qi2s0i2s0-busF== = = = = ===Q9i2s1i2s1-bus`F======Q:i2s2i2s2-bus`F======Q;usb-hosthost-drvF=Q@usb-otgotg-drvF=QBsdmmcsdmmc-pwrF=QDsdiowifi-pwrF<QEchosenTserial2:115200n8memory@60000000`@[memorygpio-leds ,gpio-ledsled-0`mk808:blue:power f>loff zdefault-onhdmi_con,hdmi-connectorbcportendpoint?Q8vcc-io,regulator-fixedvcc_io2Z2ZQAusb-host-regulator,regulator-fixed >@default host-pwrLK@LK@ Ausb-otg-regulator,regulator-fixed >Bdefaultvcc_otgLK@LK@ Asdmmc-regulator,regulator-fixed CDdefaultvcc_sd2Z2Z AQsdio-regulator,regulator-fixed CEdefault vcc_wifi2Z2Z AQ #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0mmc1clock-frequency#clock-cellsclock-output-namesregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelphandleinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modefifo-depthreset-namesmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeedvmmc-supplynon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burst#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencyportsrangesremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathlabelgpiosdefault-statelinux,default-triggerregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpioregulator-always-onstartup-delay-usvin-supply