^i8Y,(=X(,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000/spi@20070000/spi@20074000/mmc@10214000oscillator ,fixed-clockn6xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400  buscorex disabledx 5gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3$video-codec@10104000,rockchip,rk3066-vpu@   vepuvdpu (aclk_vdpuhclk_vdpuaclk_vepuhclk_vepu$cache-controller@10138000,arm,pl310-cache2@L8scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer    local-timer@1013c600,arm,cortex-a9-twd-timer    interrupt-controller@1013d000,arm,cortex-a9-gicTiLserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@  "zbaudclkapb_pclk@Lokaytxrxdefaultserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart`  #zbaudclkapb_pclkAMokaytxrxdefaultqos@1012d000,rockchip,rk3066-qossyscon L!qos@1012e000,rockchip,rk3066-qossyscon L qos@1012f000,rockchip,rk3066-qossyscon Lqos@1012f080,rockchip,rk3066-qossyscon Lqos@1012f100,rockchip,rk3066-qossyscon Lqos@1012f180,rockchip,rk3066-qossyscon Lqos@1012f200,rockchip,rk3066-qossyscon Lqos@1012f280,rockchip,rk3066-qossyscon Lusb@10180000,rockchip,rk3066-usbsnps,dwc2  otgotg@@  usb2-phyokayusb@101c0000 ,snps,dwc2  otghost usb2-phyokayethernet@10204000,rockchip,rk3066-emac @<   D hclkmacref drmiiokay # default  ethernet-phy@0 L mmc@10214000,rockchip,rk2928-dw-mshc!@  Hbiuciurx-tx.Q9resetokayEdefaultSmmc@10218000,rockchip,rk2928-dw-mshc!  Ibiuciurx-tx.R9reset disableddefaultmmc@1021c000,rockchip,rk2928-dw-mshc!  Jbiuciurx-tx.S9reset disablednand-controller@10500000,rockchip,rk2928-nfcP@  ahb disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode_@fRBrRBRB RBpower-controller!,rockchip,rk3066-power-controllerLpower-domain@7POpower-domain@6  power-domain@8!grf@20008000&,rockchip,rk3066-grfsysconsimple-mfd L usbphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyokayusb-phy@17c|QphyclkLusb-phy@188RphyclkLdma-controller@20018000,arm,pl330arm,primecell @  apb_pclkLdma-controller@2001c000,arm,pl330arm,primecell @  apb_pclk disabledi2c@2002d000,rockchip,rk3066-i2c   ( i2cP disableddefault"i2c@2002f000,rockchip,rk3066-i2c   ) Qi2cokaydefault#tps@2d-$ % %%#%/&;&G%S% ,ti,tps65910regulatorsregulator@0`vcc_rtcovrtcregulator@1`vcc_ioovioL&regulator@2`vdd_arm '`ovdd1L9regulator@3`vcc_ddr '`ovdd2regulator@5 `vcc18_cifovdig1regulator@6`vdd_11ovdig2regulator@7`vcc_25ovpllregulator@8`vcc_18ovdacregulator@9 `vcc25_hdmio vaux1regulator@10`vcca_33o vaux2regulator@11 `vcc_rmii vaux33L regulator@12 `vcc28_cifo vmmcregulator@4vdd3regulator@13 vbbpwm@20030000,rockchip,rk2928-pwm F disableddefault'pwm@20030010,rockchip,rk2928-pwm F disableddefault(watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K  3okaypwm@20050020,rockchip,rk2928-pwm  G disableddefault)pwm@20050030,rockchip,rk2928-pwm 0Gokaydefault*LGi2c@20056000,rockchip,rk3066-i2c `  * Ri2c disableddefault+i2c@2005a000,rockchip,rk3066-i2c   + Si2c disableddefault,i2c@2005e000,rockchip,rk3066-i2c   4 Ti2c disableddefault-serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @  $zbaudclkapb_pclkBNokaytxrxdefault.serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart   %zbaudclkapb_pclkCOokay txrxdefault/saradc@2006c000,rockchip,saradc   GJsaradcapb_pclkW 9saradc-apb disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk  &   txrx disableddefault0123spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk  ' @  txrx disableddefault4567dma-controller@20078000,arm,pl330arm,primecell @  apb_pclkLcpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a988"@ Oa* s* 'g83@A9cpu@1cpu,arm,cortex-a98A9display-subsystem,rockchip,display-subsystemL:;sram@10080000 ,mmio-sram Rsmp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3066-vop  aclk_vopdclk_vophclk_vop$def 9axiahbdclk disabledportL:endpoint@0Y<L@vop@1010e000,rockchip,rk3066-vop  aclk_vopdclk_vophclk_vop$ghi 9axiahbdclk disabledportL;endpoint@0Y=LAhdmi@10116000,rockchip,rk3066-hdmi`   @hclkdefault>?$  disabledportsport@0endpoint@0Y@L<endpoint@1YAL=port@1i2s@10118000,rockchip,rk3066-i2s   defaultBKi2s_clki2s_hclktxrxi disabledi2s@1011a000,rockchip,rk3066-i2s   defaultCLi2s_clki2s_hclktxrxi disabledi2s@1011c000,rockchip,rk3066-i2s   defaultDMi2s_clki2s_hclk  txrxi disabledclock-controller@20000000,rockchip,rk3066a-cru  @^_ ׄ#gрxhрxhLtimer@2000e000,snps,dw-apb-timer   .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer   ,TB timerpclktimer@2003a000,snps,dw-apb-timer   -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk  \ 9saradc-apb disabledpinctrl,rockchip,rk3066a-pinctrl Rgpio0@20034000,rockchip,gpio-bank @  6UTigpio1@2003c000,rockchip,gpio-bank   7VTiLgpio2@2003e000,rockchip,gpio-bank   8WTigpio3@20080000,rockchip,gpio-bank   9XTiLHgpio4@20084000,rockchip,gpio-bank @  :YTigpio6@2000a000,rockchip,gpio-bank   <ZTiL$pcfg-pull-defaultLFpcfg-pull-noneLEemacemac-xferEEEEEEEEL emac-mdio EEL emmcemmc-clkFemmc-cmd Femmc-rst Fhdmihdmi-hpdFL?hdmii2c-xfer EEL>i2c0i2c0-xfer EEL"i2c1i2c1-xfer EEL#i2c2i2c2-xfer EEL+i2c3i2c3-xfer EEL,i2c4i2c4-xfer EEL-pwm0pwm0-outEL'pwm1pwm1-outEL(pwm2pwm2-outEL)pwm3pwm3-outEL*spi0spi0-clkFL0spi0-cs0FL3spi0-txFL1spi0-rxFL2spi0-cs1Fspi1spi1-clkFL4spi1-cs0FL7spi1-rxFL6spi1-txFL5spi1-cs1Fuart0uart0-xfer FFLuart0-ctsFuart0-rtsFuart1uart1-xfer FFLuart1-ctsFuart1-rtsFuart2uart2-xfer F FL.uart3uart3-xfer FFL/uart3-ctsFuart3-rtsFsd0sd0-clkFLsd0-cmd FLsd0-cdFLsd0-wpFsd0-bus-width1 Fsd0-bus-width4@ F F F FLsd1sd1-clkFLsd1-cmdFLsd1-cdFLsd1-wpFsd1-bus-width1Fsd1-bus-width4@FFFFLi2s0i2s0-busFF F F F F FFFLBi2s1i2s1-bus`FFFFFFLCi2s2i2s2-bus`FFFFFFLDlan8720aphy-intELmemory@60000000memory`@vdd-log,pwm-regulator  G`vdd_logOOoB@dO*okaysdmmc-regulator,regulator-fixed `sdmmc-supply-- H!2&Lvsys-regulator,regulator-fixed`vsysLK@LK@L% #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0clock-frequency#clock-cellsclock-output-namesregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelphandleinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthreset-namesmax-frequencyvmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsrangesremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supply