9[854('4$rockchip,rk3036-evbrockchip,rk3036&!7Rockchip RK3036 Evaluation boardaliases=/i2c@20072000B/i2c@20056000G/i2c@2005a000L/mmc@1021c000R/mmc@10214000X/mmc@10218000^/serial@20060000f/serial@20064000n/serial@20068000v/spi@20074000cpuszrockchip,rk3036-smpcpu@f00cpuarm,cortex-a7 sB@@cpu@f01cpuarm,cortex-a7arm-pmuarm,cortex-a7-pmuLMdisplay-subsystemrockchip,display-subsystemtimerarm,armv7-timer0   n6oscillator fixed-clockn6%xin24m8sram@10080000 mmio-sram  E smp-sram@0rockchip,rk3066-smp-sramgpu@10090000"rockchip,rk3036-maliarm,mali-400 0Lgpgpmmupp0ppmmu0\@l@@ buscorex disabledvop@10118000rockchip,rk3036-vop +daclk_vopdclk_vophclk_vopuvw axiahbdclk disabledportendpoint@0iommu@10118300rockchip,iommu +Lvop_mmu aclkiface disabledinterrupt-controller@10139000 arm,gic-400      usb@101800002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2 otgotg@@  disabledusb@101c00002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2 otghost disabledethernet@10200000#rockchip,rk3036-emacsnps,arc-emac @ "hclkmacrefmacclk\/FdPrmiiokayYdefaultg q  u  ethernet-phy@0 mmc@102140000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc!@@<4`<4`Dbiuciu Qreset disabledmmc@102180000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc!@<4` Eswbiuciuciu-driveciu-sample Rreset disabledmmc@1021c0000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc!@ <4`<4` Guybiuciuciu-driveciu-sample rx-txYdefault gSreset disabledi2s@10220000(rockchip,rk3036-i2srockchip,rk3066-i2s"@ 3i2s_clki2s_hclkR txrxYdefaultg  disablednand-controller@10500000(rockchip,rk3036-nfcrockchip,rk2928-nfcP@ Lahbnfc\LlрgYdefault disabledclock-controller@20000000rockchip,rk3036-cru "81\l#gsyscon@20008000&rockchip,rk3036-grfsysconsimple-mfd reboot-modesyscon-reboot-mode>ERBQRB_RB oRBacodec-ana@20030000 rk3036-codec @" acodec_pclkq disabledhdmi@20034000rockchip,rk3036-inno-hdmi @@ -hpclk"Ydefaultg disabledportendpoint@0timer@20044000,rockchip,rk3036-timerrockchip,rk3288-timer @   a timerpclkpwm@20050000(rockchip,rk3036-pwmrockchip,rk2928-pwm {^Ydefaultg disabledpwm@20050010(rockchip,rk3036-pwmrockchip,rk2928-pwm {^Ydefaultg disabledpwm@20050020(rockchip,rk3036-pwmrockchip,rk2928-pwm  {^Ydefaultg disabledpwm@20050030(rockchip,rk3036-pwmrockchip,rk2928-pwm 0{^Ydefaultg disabledi2c@20056000(rockchip,rk3036-i2crockchip,rk3288-i2c ` i2cMYdefaultg okayhym8563@51haoyu,hym8563Q8%xin32ki2c@2005a000(rockchip,rk3036-i2crockchip,rk3288-i2c  i2cNYdefaultg! disabledserial@20060000&rockchip,rk3036-uartsnps,dw-apb-uart  n6MUbaudclkapb_pclkYdefault g"#$ disabledserial@20064000&rockchip,rk3036-uartsnps,dw-apb-uart @ n6NVbaudclkapb_pclkYdefaultg% disabledserial@20068000&rockchip,rk3036-uartsnps,dw-apb-uart  n6OWbaudclkapb_pclkYdefaultg&okayi2c@20072000(rockchip,rk3036-i2crockchip,rk3288-i2c   i2cLYdefaultg' disabledspi@20074000rockchip,rockchip-spi @ RAapb-pclkspi_pclk  txrxYdefaultg()*+ disabledpdma@20078000arm,pl330arm,primecell @ apb_pclk pinctrlrockchip,rk3036-pinctrl"Egpio0@2007c000rockchip,gpio-bank  $@gpio1@20080000rockchip,gpio-bank  %Agpio2@20084000rockchip,gpio-bank @ &B pcfg_pull_default-pcfg-pull-none ,pwm0pwm0-pin,pwm1pwm1-pin,pwm2pwm2-pin,pwm3pwm3-pin,sdmmcsdmmc-clk,sdmmc-cmd-sdmmc-cd-sdmmc-bus1-sdmmc-bus4@----sdiosdio-bus1 -sdio-bus4@ - - --sdio-cmd-sdio-clk ,emmcemmc-clk,emmc-cmd-emmc-bus8--------nfcflash-ale-flash-bus8--------flash-cle-flash-csn0-flash-rdn-flash-rdy-flash-wrn-emacemac-xfer - ------- emac-mdio  -- i2c0i2c0-xfer ,,'i2c1i2c1-xfer ,, i2c2i2c2-xfer ,,!i2si2s-bus`------hdmihdmi-ctl@, , , ,uart0uart0-xfer -,"uart0-cts-#uart0-rts,$uart1uart1-xfer -,%uart2uart2-xfer -,&spi-pinsspi-txd-(spi-rxd-)spi-clk-*spi-cs0-+spi-cs1-memory@60000000memory`@ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2mshc0mshc1mshc2serial0serial1serial2spienable-methoddevice_typeregresetsoperating-pointsclock-latencyclocksphandleinterruptsinterrupt-affinityportsarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesassigned-clocksassigned-clock-ratesclock-namesstatusreset-namesiommusremote-endpoint#iommu-cellsinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,grfassigned-clock-parentsmax-speedphy-modepinctrl-namespinctrl-0phyphy-reset-gpiosphy-reset-durationmax-frequencyfifo-depthbus-widthcap-mmc-highspeedrockchip,default-sample-phasedisable-wpdmasdma-namesmmc-ddr-1_8vnon-removable#sound-dai-cells#reset-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#pwm-cellsreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pins