C8;(;&amazon,omap4-kc1ti,omap4430ti,omap4 +&7Amazon Kindle Fire (first generation)chosenaliases?=/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0?B/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0?G/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0EL/ocp/interconnect@48000000/segment@200000/target-module@150000/i2c@0?Q/ocp/interconnect@48000000/segment@0/target-module@9c000/mmc@0?V/ocp/interconnect@48000000/segment@0/target-module@b4000/mmc@0?[/ocp/interconnect@48000000/segment@0/target-module@ad000/mmc@0?`/ocp/interconnect@48000000/segment@0/target-module@d1000/mmc@0?e/ocp/interconnect@48000000/segment@0/target-module@d5000/mmc@0Bj/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0Br/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0Bz/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0B/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0 /ocp/dsp/ocp/ipu@55020000cpus+cpu@0arm,cortex-a9cpucpu  'O 5acpu@1arm,cortex-a9cpusram@40304000 mmio-sram@0@~interrupt-controller@48241000arm,cortex-a9-gicH$H$ cache-controller@48242000arm,pl310-cacheH$ (6local-timer@48240600arm,cortex-a9-twd-timerH$  B  interrupt-controller@48281000ti,omap4-wugen-mpuH( ocpsimple-pm-busM$ +[l3-noc@44000000ti,omap4-l3-nocDD EB  interconnect@4a300000ti,omap4-l4-wkupsimple-pm-busM  fckJ0J0J0 baplaia0+$[J0J1J2segment@0simple-pm-bus+[`` @@PPtarget-module@4000ti,sysc-omap2ti,sysc@@ brevsyscl 0fck+ [@counter@0ti,omap-counter32k target-module@6000ti,sysc-omap4ti,sysc`brev+ [` prm@0ti,omap4-prmsimple-bus  B + [ clocks+sys_clkin_ck@110z ti,mux-clock abe_dpll_bypass_clk_mux_ck@108z ti,mux-clock9abe_dpll_refclk_mux_ck@10cz ti,mux-clock 8dbgclk_mux_ckzfixed-factor-clockl4_wkup_clk_mux_ck@108z ti,mux-clocksyc_clk_div_ck@100zti,divider-clockusim_ck@1858zti,divider-clockXusim_fclk@1858zti,gate-clockXtrace_clk_div_ckzti,clkdm-gate-clock bandgap_fclk@1888zti,gate-clockclockdomainsemu_sys_clkdmti,clockdomainl4_wkup_cm@1800 ti,omap4-cm+ [clk@20 ti,clkctrl \z emu_sys_cm@1a00 ti,omap4-cm+ [clk@20 ti,clkctrl zprm@300#ti,omap4-prm-instti,omap-prm-inst|prm@400#ti,omap4-prm-instti,omap-prm-instcprm@500#ti,omap4-prm-instti,omap-prm-instprm@600#ti,omap4-prm-instti,omap-prm-instprm@700#ti,omap4-prm-instti,omap-prm-inst4prm@f00#ti,omap4-prm-instti,omap-prm-instprm@1000#ti,omap4-prm-instti,omap-prm-instprm@1100#ti,omap4-prm-instti,omap-prm-inst@prm@1200#ti,omap4-prm-instti,omap-prm-instprm@1300#ti,omap4-prm-instti,omap-prm-instprm@1400#ti,omap4-prm-instti,omap-prm-instprm@1600#ti,omap4-prm-instti,omap-prm-instprm@1700#ti,omap4-prm-instti,omap-prm-inst prm@1900#ti,omap4-prm-instti,omap-prm-instprm@1b00#ti,omap4-prm-instti,omap-prm-inst@target-module@a000ti,sysc-omap4ti,syscbrev+ [scrm@0ti,omap4-scrm clocks+auxclk0_src_gate_ck@310z ti,composite-no-wait-gate-clockauxclk0_src_mux_ck@310zti,composite-mux-clock auxclk0_src_ckzti,composite-clockauxclk0_ck@310zti,divider-clock.auxclk1_src_gate_ck@314z ti,composite-no-wait-gate-clockauxclk1_src_mux_ck@314zti,composite-mux-clock  auxclk1_src_ckzti,composite-clock !auxclk1_ck@314zti,divider-clock!/auxclk2_src_gate_ck@318z ti,composite-no-wait-gate-clock"auxclk2_src_mux_ck@318zti,composite-mux-clock #auxclk2_src_ckzti,composite-clock"#$auxclk2_ck@318zti,divider-clock$0auxclk3_src_gate_ck@31cz ti,composite-no-wait-gate-clock%auxclk3_src_mux_ck@31czti,composite-mux-clock &auxclk3_src_ckzti,composite-clock%&'auxclk3_ck@31czti,divider-clock'1auxclk4_src_gate_ck@320z ti,composite-no-wait-gate-clock (auxclk4_src_mux_ck@320zti,composite-mux-clock  )auxclk4_src_ckzti,composite-clock()*auxclk4_ck@320zti,divider-clock* 2auxclk5_src_gate_ck@324z ti,composite-no-wait-gate-clock$+auxclk5_src_mux_ck@324zti,composite-mux-clock $,auxclk5_src_ckzti,composite-clock+,-auxclk5_ck@324zti,divider-clock-$3auxclkreq0_ck@210z ti,mux-clock./0123auxclkreq1_ck@214z ti,mux-clock./0123auxclkreq2_ck@218z ti,mux-clock./0123auxclkreq3_ck@21cz ti,mux-clock./0123auxclkreq4_ck@220z ti,mux-clock./0123 auxclkreq5_ck@224z ti,mux-clock./0123$clockdomainstarget-module@c000ti,sysc-omap4ti,sysc brevsyscl+ [scm@c000ti,omap4-scm-wkupsegment@10000simple-pm-bus+x[@@PPtarget-module@0ti,sysc-omap2ti,syscbrevsyscsyssl   fckdbclk+ [gpio@0ti,omap4-gpio B$4target-module@4000ti,sysc-omap2ti,sysc@@@brevsyscsyss"l fck+ [@wdt@0ti,omap4-wdtti,omap3-wdt BPtarget-module@8000ti,sysc-omap2-timerti,syscbrevsyscsyss' l fck+ [@Ttimer@0ti,omap3430-timer fcktimer_sys_ck B%_ n ~target-module@c000ti,sysc-omap2ti,syscbrevsyscsyss' l Xfck+ [keypad@0ti,omap4-keypad Bxbmputarget-module@e000ti,sysc-omap4ti,sysc brevsyscl+ [pinmux@40 ti,omap4-padconfpinctrl-single@8+pinmux_twl6030_wkup_pinsssegment@20000simple-pm-bus+[``  00@@PPpptarget-module@0ti,sysc disabled+ [target-module@2000ti,sysc disabled+ [ target-module@4000ti,sysc disabled+ [@target-module@6000ti,sysc disabled+0[`p 0interconnect@4a000000ti,omap4-l4-cfgsimple-pm-busM4 5fckJJJ baplaia0+T[JJJJ J (J(0J0segment@0simple-pm-bus+[ 00@@PP``pp@  00 ``pp @@PPtarget-module@2000ti,sysc-omap4ti,sysc   brevsyscl+ [ scm@0ti,omap4-scm-coresimple-bus+ [scm_conf@0syscon+control-phy@300ti,control-phy-usb2bpowergcontrol-phy@33cti,control-phy-otghs<botghs_controletarget-module@4000ti,sysc-omap4ti,sysc@brev+ [@cm1@0ti,omap4-cm1simple-bus + [ clocks+extalt_clkin_ckz fixed-clockDpad_clks_src_ckz fixed-clock6pad_clks_ck@108zti,gate-clock6pad_slimbus_core_clks_ckz fixed-clocksecure_32k_clk_src_ckz fixed-clockslimbus_src_clkz fixed-clock7slimbus_clk@108zti,gate-clock7 sys_32k_ckz fixed-clockvirt_12000000_ckz fixed-clock virt_13000000_ckz fixed-clock]@ virt_16800000_ckz fixed-clockYvirt_19200000_ckz fixed-clock$virt_26000000_ckz fixed-clockvirt_27000000_ckz fixed-clockvirt_38400000_ckz fixed-clockItie_low_clock_ckz fixed-clockutmi_phy_clkout_ckz fixed-clockxclk60mhsp1_ckz fixed-clock`xclk60mhsp2_ckz fixed-clockaxclk60motg_ckz fixed-clockdpll_abe_ck@1e0zti,omap4-dpll-m4xen-clock89:dpll_abe_x2_ck@1f0zti,omap4-dpll-x2-clock:;dpll_abe_m2x2_ck@1f0zti,divider-clock; <abe_24m_fclkzfixed-factor-clock<abe_clk@108zti,divider-clock<3dpll_abe_m3x2_ck@1f4zti,divider-clock; =core_hsd_byp_clk_mux_ck@12cz ti,mux-clock=,>dpll_core_ck@120zti,omap4-dpll-core-clock> $,(?dpll_core_x2_ckzti,omap4-dpll-x2-clock?@dpll_core_m6x2_ck@140zti,divider-clock@ @dpll_core_m2_ck@130zti,divider-clock? 0Addrphy_ckzfixed-factor-clockAdpll_core_m5x2_ck@13czti,divider-clock@ <Bdiv_core_ck@100zti,divider-clockBMdiv_iva_hs_clk@1dczti,divider-clockB3Fdiv_mpu_hs_clk@19czti,divider-clockB3Ldpll_core_m4x2_ck@138zti,divider-clock@ 8Cdll_clk_div_ckzfixed-factor-clockCdpll_abe_m2_ck@1f0zti,divider-clock:Pdpll_core_m3x2_gate_ck@134z ti,composite-no-wait-gate-clock@4Ddpll_core_m3x2_div_ck@134zti,composite-divider-clock@4Edpll_core_m3x2_ckzti,composite-clockDEdpll_core_m7x2_ck@144zti,divider-clock@ Diva_hsd_byp_clk_mux_ck@1acz ti,mux-clockFGdpll_iva_ck@1a0zti,omap4-dpll-clockGnHI7Hdpll_iva_x2_ckzti,omap4-dpll-x2-clockHIdpll_iva_m4x2_ck@1b8zti,divider-clockI nJI~Jdpll_iva_m5x2_ck@1bczti,divider-clockI nKI] Kdpll_mpu_ck@160zti,omap4-dpll-clockL`dlhdpll_mpu_m2_ck@170zti,divider-clock pper_hs_clk_div_ckzfixed-factor-clock=Qusb_hs_clk_div_ckzfixed-factor-clock=Wl3_div_ck@100zti,divider-clockMNl4_div_ck@100zti,divider-clockNlp_clk_div_ckzfixed-factor-clock<mpu_periphclkzfixed-factor-clockocp_abe_iclk@528zti,divider-clock O(per_abe_24m_fclkzfixed-factor-clockPdummy_ckz fixed-clockclockdomainsmpuss_cm@300 ti,omap4-cm+ [clk@20 ti,clkctrl z}tesla_cm@400 ti,omap4-cm+ [clk@20 ti,clkctrl zbabe_cm@500 ti,omap4-cm+ [clk@20 ti,clkctrl lzOtarget-module@8000ti,sysc-omap4ti,syscbrev+ [ cm2@0ti,omap4-cm2simple-bus + [ clocks+per_hsd_byp_clk_mux_ck@14cz ti,mux-clockQLRdpll_per_ck@140zti,omap4-dpll-clockR@DLHSdpll_per_m2_ck@150zti,divider-clockSP[dpll_per_x2_ck@150zti,omap4-dpll-x2-clockSPTdpll_per_m2x2_ck@150zti,divider-clockT PZdpll_per_m3x2_gate_ck@154z ti,composite-no-wait-gate-clockTTUdpll_per_m3x2_div_ck@154zti,composite-divider-clockTTVdpll_per_m3x2_ckzti,composite-clockUVdpll_per_m4x2_ck@158zti,divider-clockT Xdpll_per_m5x2_ck@15czti,divider-clockT \dpll_per_m6x2_ck@160zti,divider-clockT `Ydpll_per_m7x2_ck@164zti,divider-clockT ddpll_usb_ck@180zti,omap4-dpll-j-type-clockWXdpll_usb_clkdcoldo_ck@1b4zti,fixed-factor-clockX^ kdpll_usb_m2_ck@190zti,divider-clockX \ducati_clk_mux_ck@100z ti,mux-clockMYfunc_12m_fclkzfixed-factor-clockZfunc_24m_clkzfixed-factor-clock[func_24mc_fclkzfixed-factor-clockZfunc_48m_fclk@108zti,divider-clockZfunc_48mc_fclkzfixed-factor-clockZfunc_64m_fclk@108zti,divider-clockfunc_96m_fclk@108zti,divider-clockZinit_60m_fclk@104zti,divider-clock\_per_abe_nc_fclk@108zti,divider-clockPusb_phy_cm_clk32k@640zti,gate-clock@hclockdomainsl3_init_clkdmti,clockdomainXl4_ao_cm@600 ti,omap4-cm+ [clk@20 ti,clkctrl zjl3_1_cm@700 ti,omap4-cm+ [clk@20 ti,clkctrl zl3_2_cm@800 ti,omap4-cm+ [clk@20 ti,clkctrl zducati_cm@900 ti,omap4-cm + [ clk@20 ti,clkctrl zl3_dma_cm@a00 ti,omap4-cm + [ clk@20 ti,clkctrl z]l3_emif_cm@b00 ti,omap4-cm + [ clk@20 ti,clkctrl zd2d_cm@c00 ti,omap4-cm + [ clk@20 ti,clkctrl zil4_cfg_cm@d00 ti,omap4-cm + [ clk@20 ti,clkctrl z5l3_instr_cm@e00 ti,omap4-cm+ [clk@20 ti,clkctrl $z ivahd_cm@f00 ti,omap4-cm+ [clk@20 ti,clkctrl ziss_cm@1000 ti,omap4-cm+ [clk@20 ti,clkctrl zll3_dss_cm@1100 ti,omap4-cm+ [clk@20 ti,clkctrl zl3_gfx_cm@1200 ti,omap4-cm+ [clk@20 ti,clkctrl zl3_init_cm@1300 ti,omap4-cm+ [clk@20 ti,clkctrl z^l4_per_cm@1400 ti,omap4-cm+ [clock@20ti,clkctrl-l4-perti,clkctrl Dzmclock@1a0 ti,clkctrl-l4-secureti,clkctrl<zvtarget-module@56000ti,sysc-omap2ti,sysc``,`(brevsyscsyss# y l ]fck+ [`dma-controller@0ti,omap4430-sdmati,omap-sdma0B   wtarget-module@58000ti,sysc-omap2ti,syscbrevsyscsyss#yl ^fck+ [Phsi@0 ti,omap4-hsi@Pbsysgdd ^hsi_fck BGgdd_mpu+ [@hsi-port@2000ti,omap4-hsi-port (btxrx BChsi-port@3000ti,omap4-hsi-port08btxrx BDtarget-module@5e000ti,sysc disabled+ [ target-module@62000ti,sysc-omap2ti,sysc   brevsyscsyss l ^Hfck+ [ usbhstll@0 ti,usbhs-tll BNtarget-module@64000ti,sysc-omap4ti,sysc@@@brevsyscsyssyl ^8fck+ [@usbhshost@0ti,usbhs-host+ [ _`a3refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2ohci@800ti,ohci-omap3 BLehci@c00 ti,ehci-omap  BMtarget-module@66000ti,sysc-omap2ti,sysc```brevsyscsyss l bfckMccrstctrl+ [`mmu@0ti,omap4-iommu Bsegment@80000simple-pm-bus+[      @@PP``pp` `p p        target-module@29000ti,sysc disabled+ [target-module@2b000ti,sysc-omap2ti,syscbrevsyscsyss yl ^@fck+ [usb_otg_hs@0ti,omap4-musbB\]mcdmadd usb2-phy  'e3defaultAfKZ_2target-module@2d000ti,sysc-omap2ti,syscbrevsyscsyss l ^fck+ [ocp2scp@0ti,omap-ocp2scp+ [usb2phy@80 ti,omap-usb2X'ghwkupclkedtarget-module@36000ti,sysc-omap2ti,sysc```brevsyscsyssl ifck+ [`target-module@4d000ti,sysc-omap2ti,syscbrevsyscsyssl ifck+ [target-module@59000ti,sysc-omap4-srti,sysc8bsyscl jfck+ [smartreflex@0ti,omap4-smartreflex-mpu Btarget-module@5b000ti,sysc-omap4-srti,sysc8bsyscl jfck+ [smartreflex@0ti,omap4-smartreflex-iva Bftarget-module@5d000ti,sysc-omap4-srti,sysc8bsyscl jfck+ [smartreflex@0ti,omap4-smartreflex-core Btarget-module@60000ti,sysc disabled+ [target-module@74000ti,sysc-omap4ti,sysc@@ brevsysc l 5fck+ [@mailbox@0ti,omap4-mailbox Bp|mbox-ipu  mbox-dsp  target-module@76000ti,sysc-omap2ti,sysc```brevsyscsyss l 5fck+ [`spinlock@0ti,omap4-hwspinlocksegment@100000simple-pm-bus+`[  00target-module@0ti,sysc-omap4ti,sysc brevsyscl+ [pinmux@40 ti,omap4-padconfpinctrl-single@+3defaultopinmux_uart3_pinsnpinmux_i2c1_pinsqpinmux_i2c2_pinsupinmux_i2c3_pinsppinmux_i2c4_pins{pinmux_mmc2_pinsP  BDypinmux_usb_otg_hs_pinsTVXfpinmux_twl6030_pins^Aromap4_padconf_global@5a0sysconsimple-busp+ [pkpbias_regulator@60ti,pbias-omap4ti,pbias-omap`kpbias_mmc_omap4pbias_mmc_omap4w@-xtarget-module@2000ti,sysc disabled+ [ target-module@8000ti,sysc disabled+ [target-module@a000ti,sysc-omap4ti,sysc brevsysc y l  lfck+ [segment@180000simple-pm-bus+segment@200000simple-pm-bus+h[!!  @ @P P` `p p ! 0!0  !!`!`p!p@!@P!P!!""`"`p"p""""!!target-module@4000ti,sysc disabled+ [@target-module@6000ti,sysc disabled+ [`target-module@a000ti,sysc disabled+ [target-module@c000ti,sysc disabled+ [target-module@10000ti,sysc disabled+ [target-module@12000ti,sysc disabled+ [ target-module@14000ti,sysc disabled+ [@target-module@16000ti,sysc disabled+ [`target-module@18000ti,sysc disabled+ [target-module@1c000ti,sysc disabled+ [target-module@1e000ti,sysc disabled+ [target-module@20000ti,sysc disabled+ [target-module@26000ti,sysc disabled+ [`target-module@28000ti,sysc disabled+ [target-module@2a000ti,sysc disabled+ [segment@280000simple-pm-bus+segment@300000simple-pm-bus+[042@@2@ `2`p2p2232 2@target-module@0ti,sysc disabled+x[@@@ ``pp @interconnect@48000000ti,omap4-l4-persimple-pm-busM mfck0HHHHHHbaplaia0ia1ia2ia3+[H H segment@0simple-pm-bus+[  00@@PP``ppPP``pp  00 ` ` p p``pp``pp             @ @ ` ` @     0 0 @ @ P P        P P ` `  0 0 P Ptarget-module@20000ti,sysc-omap2ti,syscPTXbrevsyscsyssl m0fck+ [serial@0ti,omap4-uart BJl3defaultAnJotarget-module@32000ti,sysc-omap2-timerti,sysc   brevsyscsyss' l mfck+ [ timer@0ti,omap3430-timermfcktimer_sys_ck B&target-module@34000ti,sysc-omap4-timerti,sysc@@ brevsyscl m fck+ [@timer@0ti,omap4430-timerm fcktimer_sys_ck B'target-module@36000ti,sysc-omap4-timerti,sysc`` brevsyscl m(fck+ [`timer@0ti,omap4430-timerm(fcktimer_sys_ck B(target-module@3e000ti,sysc-omap4-timerti,sysc brevsyscl m0fck+ [timer@0ti,omap4430-timerm0fcktimer_sys_ck B-/target-module@40000ti,sysc disabled+ [target-module@55000ti,sysc-omap2ti,syscPPQbrevsyscsysslm@m@ fckdbclk+ [Pgpio@0ti,omap4-gpio B$4target-module@57000ti,sysc-omap2ti,syscppqbrevsyscsysslmHmH fckdbclk+ [pgpio@0ti,omap4-gpio B$4target-module@59000ti,sysc-omap2ti,syscbrevsyscsysslmPmP fckdbclk+ [gpio@0ti,omap4-gpio B $4target-module@5b000ti,sysc-omap2ti,syscbrevsyscsysslmXmX fckdbclk+ [gpio@0ti,omap4-gpio B!$4target-module@5d000ti,sysc-omap2ti,syscbrevsyscsysslm`m` fckdbclk+ [gpio@0ti,omap4-gpio B"$4target-module@60000ti,sysc-omap2ti,syscbrevsyscsyssl mfck+ [i2c@0 ti,omap4-i2c B=+3defaultAptarget-module@6a000ti,sysc-omap2ti,syscPTXbrevsyscsyssl m fck+ [serial@0ti,omap4-uart BHltarget-module@6c000ti,sysc-omap2ti,syscPTXbrevsyscsyssl m(fck+ [serial@0ti,omap4-uart BIltarget-module@6e000ti,sysc-omap2ti,syscPTXbrevsyscsyssl m8fck+ [serial@0ti,omap4-uart BFltarget-module@70000ti,sysc-omap2ti,syscbrevsyscsyssl mfck+ [i2c@0 ti,omap4-i2c B8+3defaultAqtwl@48H B ti,twl60303defaultArspowerti,twl6030-power<rtcti,twl4030-rtcB regulator-vaux1ti,twl6030-vaux1B@-zregulator-vaux2ti,twl6030-vaux2O*regulator-vaux3ti,twl6030-vaux3B@-regulator-vmmcti,twl6030-vmmcO-regulator-vppti,twl6030-vppw@&%regulator-vusimti,twl6030-vusimO,@ regulator-vdacti,twl6030-vdacregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxioWregulator-vusbti,twl6030-vusbtregulator-v1v8ti,twl6030-v1v8Wregulator-v2v1ti,twl6030-v2v1Wusb-comparatorti,twl6030-usbB ktpwmti,twl6030-pwmvpwmledti,twl6030-pwmledvgpadcti,twl6030-gpadcBtarget-module@72000ti,sysc-omap2ti,sysc   brevsyscsyssl mfck+ [ i2c@0 ti,omap4-i2c B9+3defaultAutarget-module@76000ti,sysc-omap4ti,sysc`` brevsyscl mfck+ [`target-module@78000ti,sysc-omap2ti,syscbrevsyscsyss l m8fck+ [elm@0ti,am3352-elm  B disabledtarget-module@86000ti,sysc-omap2-timerti,sysc```brevsyscsyss' l mfck+ [`timer@0ti,omap3430-timermfcktimer_sys_ck B./target-module@88000ti,sysc-omap4-timerti,sysc brevsyscl mfck+ [timer@0ti,omap4430-timermfcktimer_sys_ck B//target-module@90000ti,sysc-omap2ti,sysc   brevsyscl v fck+ [ rng@0 ti,omap4-rng  B4target-module@96000ti,sysc-omap2ti,sysc `bsysc l mfck+ [ `mcbsp@0ti,omap4-mcbspbmpu Bcommonww txrx disabledtarget-module@98000ti,sysc-omap4ti,sysc   brevsyscl mfck+ [ spi@0ti,omap4-mcspi BA+@w#w$w%w&w'w(w)w* tx0rx0tx1rx1tx2rx2tx3rx3target-module@9a000ti,sysc-omap4ti,sysc   brevsyscl mfck+ [ spi@0ti,omap4-mcspi BB+ w+w,w-w.tx0rx0tx1rx1target-module@9c000ti,sysc-omap4ti,sysc   brevsyscyl ^fck+ [ mmc@0ti,omap4-hsmmc BSw=w>txrxx disabledtarget-module@9e000ti,sysc disabled+ [ target-module@a2000ti,sysc disabled+ [ target-module@a4000ti,sysc disabled+[ @ Ptarget-module@a5000ti,sysc-omap2ti,sysc P0 P4 P8brevsyscsyssl vfck+ [ Pdes@0 ti,omap4-des BRwuwttxrxtarget-module@a8000ti,sysc disabled+ [ @target-module@ad000ti,sysc-omap4ti,sysc   brevsyscyl mfck+ [ mmc@0ti,omap4-hsmmc B^wMwNtxrx disabledtarget-module@b0000ti,sysc disabled+ [ target-module@b2000ti,sysc-omap2ti,sysc   brevsyscsyss@ mhfck+ [ 1w@0 ti,omap3-1w B:target-module@b4000ti,sysc-omap4ti,sysc @ @ brevsyscyl ^fck+ [ @mmc@0ti,omap4-hsmmc BVw/w0txrx3defaultAyz target-module@b8000ti,sysc-omap4ti,sysc   brevsyscl mfck+ [ spi@0ti,omap4-mcspi B[+wwtx0rx0target-module@ba000ti,sysc-omap4ti,sysc   brevsyscl mfck+ [ spi@0ti,omap4-mcspi B0+wFwGtx0rx0target-module@d1000ti,sysc-omap4ti,sysc   brevsyscyl mfck+ [ mmc@0ti,omap4-hsmmc B`w9w:txrx disabledtarget-module@d5000ti,sysc-omap4ti,sysc P P brevsyscyl m@fck+ [ Pmmc@0ti,omap4-hsmmc B;w;w<txrxsegment@200000simple-pm-bus+[55target-module@150000ti,sysc-omap2ti,syscbrevsyscsyssl mfck+ [i2c@0 ti,omap4-i2c B>+3defaultA{target-module@48210000ti,sysc-omap4-simpleti,syscM| }fck+ [H!mpu ti,omap4-mpu~interconnect@40100000ti,omap4-l4-abesimple-pm-bus@@blaapM+[@IIsegment@0simple-pm-bus+0[  00@@PP``pp  00      IIIII I I0I0I@I@IPIPI`I`IpIpIIIIIIIIIIIIIIIII I I0I0IIIIIIIIIIIIIIIIIIIII I I I I I I I III I target-module@22000ti,sysc-omap2ti,sysc bsysc l O(fck+[ I I mcbsp@0ti,omap4-mcbspI bmpudma Bcommonw!w"txrx disabledtarget-module@24000ti,sysc-omap2ti,sysc@bsysc l O0fck+[@I@I@mcbsp@0ti,omap4-mcbspI@bmpudma Bcommonwwtxrx disabledtarget-module@26000ti,sysc-omap2ti,sysc`bsysc l O8fck+[`I`I`mcbsp@0ti,omap4-mcbspI`bmpudma Bcommonwwtxrx disabledtarget-module@28000ti,sysc-mcaspti,sysc brevsyscl O fck+[IItarget-module@2a000ti,sysc disabled+[IItarget-module@2e000ti,sysc-omap4ti,sysc brevsyscl Ofck+[IIdmic@0ti,omap4-dmicIbmpudma BrwCup_link disabledtarget-module@30000ti,sysc-omap2ti,syscbrevsyscsyss"l Ohfck+[IIwdt@0ti,omap4-wdtti,omap3-wdt BPtarget-module@32000ti,sysc-omap4ti,sysc   brevsyscl Ofck+[ I I  disabledmcpdm@0ti,omap4-mcpdmI bmpudma BpwAwBup_linkdn_linktarget-module@38000ti,sysc-omap4-timerti,sysc brevsyscl OHfck+[IItimer@0ti,omap4430-timerIOHfcktimer_sys_ck B)target-module@3a000ti,sysc-omap4-timerti,sysc brevsyscl OPfck+[IItimer@0ti,omap4430-timerIOPfcktimer_sys_ck B*target-module@3c000ti,sysc-omap4-timerti,sysc brevsyscl OXfck+[IItimer@0ti,omap4430-timerIOXfcktimer_sys_ck B+target-module@3e000ti,sysc-omap4-timerti,sysc brevsyscl O`fck+[IItimer@0ti,omap4430-timerIO`fcktimer_sys_ck B,/target-module@80000ti,sysc disabled+[IItarget-module@a0000ti,sysc disabled+[ I I target-module@c0000ti,sysc disabled+[ I I target-module@f1000ti,sysc-omap4ti,sysc brevsyscy l Ofck+[IItarget-module@50000000ti,sysc-omap2ti,syscPPPbrevsyscsyss l) fck+[PP@gpmc@50000000ti,omap4430-gpmcP+ Bwrxtx<HNfck$4target-module@52000000ti,sysc-omap4ti,syscRR brevsyscyl M lfck+ [Rtarget-module@54000000ti,sysc-omap4-simpleti,syscM fck+ [Tpmuarm,cortex-a9-pmutarget-module@55082000ti,sysc-omap2ti,syscU U U brevsyscsyss l fck4rstctrl [U +mmu@0ti,omap4-iommu BdZtarget-module@4012c000ti,sysc-omap4ti,sysc@@ brevsyscl O@fck+[@IItarget-module@4e000000ti,sysc-omap2ti,syscNN brevsysc l [N+dmm@0 ti,omap4-dmm Bqtarget-module@4c000000ti,sysc-omap4-simpleti,syscLbrev fckT+ [Lemif@0 ti,emif-4d Bnpytarget-module@4d000000ti,sysc-omap4-simpleti,syscMbrev fckT+ [Memif@0 ti,emif-4d Bopydsp ti,omap4-dsp c bomap4-dsp-fw.xe64T disabledipu@55020000 ti,omap4-ipuUbl2ram44 omap4-ipu-fw.xem3 disabledtarget-module@4b501000ti,sysc-omap2ti,syscKPKPKPbrevsyscsyssl vfck+ [KPaes@0 ti,omap4-aes BUwowntxrxtarget-module@4b701000ti,sysc-omap2ti,syscKpKpKpbrevsyscsyssl vfck+ [Kpaes@0 ti,omap4-aes B@wrwqtxrxtarget-module@4b100000ti,sysc-omap3-shamti,syscKKKbrevsyscsyss l v(fck+ [Ksham@0ti,omap4-sham B3wwrxregulator-abb-mpu ti,abb-v2abb_mpu+2 okayJ0{J0`bbase-addressint-addressxO1regulator-abb-iva ti,abb-v2abb_iva+߀2  disabledJ0{J0`bbase-addressint-addresstarget-module@56000000ti,sysc-omap4ti,syscVV brevsyscylM fck+ [VnIO~target-module@58000000ti,sysc-omap2ti,syscXX brevsyssM0 fckhdmi_clksys_clktv_clk+ [Xdss@0 ti,omap4-dss disabled fck+ [target-module@1000ti,sysc-omap2ti,syscbrevsyscsyss l y  fcksys_clk+ [dispc@0ti,omap4-dispc B fcktarget-module@2000ti,sysc-omap2ti,sysc   brevsyscsyss l  fcksys_clk+ [ encoder@0 disabledNfckicktarget-module@3000ti,sysc-omap2ti,sysc0brev sys_clk+ [0encoder@0ti,omap4-venc disabled fcktarget-module@4000ti,sysc-omap2ti,sysc@@@brevsyscsyss l+ [@encoder@0 ti,omap4-dsi@ bprotophypll B5 disabled  fcksys_clk+target-module@5000ti,sysc-omap2ti,syscPPPbrevsyscsyss l+ [Pencoder@0 ti,omap4-dsi@ bprotophypll BT disabled  fcksys_clk+target-module@6000ti,sysc-omap4ti,sysc`` brevsyscl  fckdss_clk+ [` encoder@0ti,omap4-hdmi bwppllphycore Be disabled  fcksys_clkwL audio_txtarget-module@5a000000ti,sysc-omap4ti,syscZZ brevsysc y lMrstctrl fck+[ZZ[[iva ti,ivahdbandgap@4a002260J"`J#,ti,omap4430-bandgap %+thermal-zonescpu_thermalAWeuN tripscpu_alertpassivecpu_critH criticalcooling-mapsmap0 memory@80000000memory led-controller pwm-ledsled-1green w5led-2orange w5 compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3mmc0mmc1mmc2mmc3mmc4serial0serial1serial2serial3rproc0rproc1device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-points#cooling-cellsphandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptspower-domainsrangesreg-namesti,sysc-sidle#clock-cellsti,index-starts-at-oneti,bit-shiftclock-multclock-divti,max-divti,dividers#power-domain-cells#reset-cellsti,sysc-maskti,syss-maskti,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parents#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsstatusclock-frequencyti,autoidle-shiftti,invert-autoidle-bitti,index-power-of-twoassigned-clock-ratesti,clock-divti,clock-multti,sysc-midle#dma-cellsdma-channelsdma-requestsinterrupt-namesremote-wakeup-connectedresetsreset-names#iommu-cellsusb-phyphysphy-namesmultipointnum-epsram-bitsctrl-modulepinctrl-namespinctrl-0interface-typemodepower#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,sysc-delay-usinterrupts-extendedti,timer-pwmti,system-power-controllerregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,buffer-sizedmasdma-namesti,spi-num-csti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplyti,non-removablebus-widthsramti,timer-dspti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsti,iommu-bus-err-backphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertti,bootregiommusfirmware-namemboxesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infogpios#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-devicelabelpwmsmax-brightness