$8(netxeon,r89rockchip,rk3288& 7Netxeon R89aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbcpu-opp-tableoperating-points-v2jbopp-126000000u| opp-216000000u | opp-312000000u| opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ| opp-1608000000u_"|pbus simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkbdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkbRreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem5 mmc@ff0c0000rockchip,rk3288-dw-mshc;р 5Drvbiuciuciu-driveciu-sampleI  @Tresetokay`j|default mmc@ff0d0000rockchip,rk3288-dw-mshc;р 5Eswbiuciuciu-driveciu-sampleI ! @Treset disabledmmc@ff0e0000rockchip,rk3288-dw-mshc;р 5Ftxbiuciuciu-driveciu-sampleI "@Treset disabledmmc@ff0f0000rockchip,rk3288-dw-mshc;р 5Guybiuciuciu-driveciu-sampleI #@Treset disabledsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW Tsaradc-apbokayspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -default disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .default  disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault! disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault" disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault# disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault$okayserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclktxrxdefault%okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclktxrxdefault&okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault'okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclktxrxdefault(okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclk  txrxdefault)okaythermal-zonesreserve_thermal5C*cpu_thermald5C*tripscpu_alert0Sp_passiveb+cpu_alert1S$_passiveb,cpu_critS__ criticalcooling-mapsmap0j+0omap1j,0ogpu_thermald5C*tripsgpu_alert0Sp_passiveb-gpu_critS__ criticalcooling-mapsmap0j- o.tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk Ttsadc-apbinitdefaultsleep/~0/1sokayb*ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq185fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Tstmmacethok2rgmii"input /3? U'B@jz4default50usb@ff500000 generic-ehciP 56usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost7 usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otgotg@@ 8 usb2-phyokayusb@ff5c0000 generic-ehci\ 5 disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault9okaypmic@40silergy,syr827@VDD_CPU-,I Papy@:b pmic@41silergy,syr828AVDD_GPU-,I Papy@:rtc@51haoyu,hym8563Qxin32k&;default<pmic@5aactive-semi,act8846Zdefault=>regulatorsREG1VCC_DDRIOaOREG2VCC_IOI2Za2ZbwREG3VDD_LOGIB@aB@REG4VCC_20IaREG5 VCCIO_SDI2Za2ZbREG6 VDD10_LCDIB@aB@REG7VCC_WLI2Za2ZREG8VCCA_33I2Za2ZREG9VCC_LANI2Za2Zb2REG10VDD_10IB@aB@REG11VCC_18Iw@aw@bREG12 VCC18_LCDIw@aw@i2c@ff660000rockchip,rk3288-i2cf =i2c5Ndefault? disabledpwm@ff680000rockchip,rk3288-pwmhdefault@5_pwmokaypwm@ff680010rockchip,rk3288-pwmhdefaultA5_pwm disabledpwm@ff680020rockchip,rk3288-pwmh defaultB5_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultC5_pwm disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerjhz bUpd_vio@9 5chgfdehilkj$DEFGHIJKLpd_hevc@11 5opMNpd_video@12 5Opd_gpu@13 5PQreboot-modesyscon-reboot-modeRBRBRB .RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv1:Hjjk$G#gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb1edp-phyrockchip,rk3288-dp-phy5h24m\ disabledbeio-domains"rockchip,rk3288-io-voltage-domain disabledusbphyrockchip,rk3288-usb-phyokayusb-phy@320\ 5]phyclk Tphy-resetb8usb-phy@334\45^phyclk Tphy-resetb6usb-phy@348\H5_phyclk Tphy-resetb7watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifg5T mclkhclkRtx 6defaultS1 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sg 55Ri2s_clki2s_hclkRRtxrxdefaultTx disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk Tcrypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P isp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkU ilm Tcoreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopU def TaxiahbdclkVokayportb endpoint@0Wbhendpoint@1Xbfendpoint@2Yb`endpoint@3Zbciommu@ff930300rockchip,iommu  vopb_mmu5 aclkifaceU okaybVvop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopU  Taxiahbdclk[okayportb endpoint@0\biendpoint@1]bgendpoint@2^baendpoint@3_bdiommu@ff940300rockchip,iommu  vopl_mmu5 aclkifaceU okayb[mipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkU 1 disabledportsportendpoint@0`bYendpoint@1ab^lvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcbU 1 disabledportsport@0endpoint@0cbZendpoint@1db_dp@ff970000rockchip,rk3288-dp@ b5icdppclkedpoTdp1 disabledportsport@0endpoint@0fbXendpoint@1gb]hdmi@ff980000rockchip,rk3288-dw-hdmig1 g5hmniahbisfrcecU okayportsportendpoint@0hbWendpoint@1ib\video-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu5 aclkhclkjU iommu@ff9a0800rockchip,iommu vpu_mmu5 aclkifaceU bjiommu@ff9c0440rockchip,iommu @@@ o hevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5kU  disabledb.gpu-opp-tableoperating-points-v2bkopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000syscon bPqos@ffaa0080syscon bQqos@ffad0000syscon bEqos@ffad0100syscon bFqos@ffad0180syscon bGqos@ffad0400syscon bHqos@ffad0480syscon bIqos@ffad0500syscon bDqos@ffad0800syscon bJqos@ffad0880syscon bKqos@ffad0900syscon bLqos@ffae0000syscon bOqos@ffaf0000syscon bMqos@ffaf0080syscon bNefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400@ @ `   bpinctrlrockchip,rk3288-pinctrl1gpio0@ff750000rockchip,gpio-banku Q5@ 0b;gpio1@ff780000rockchip,gpio-bankx R5A 0gpio2@ff790000rockchip,gpio-banky S5B 0gpio3@ff7a0000rockchip,gpio-bankz T5C 0gpio4@ff7b0000rockchip,gpio-bank{ U5D 0b3gpio5@ff7c0000rockchip,gpio-bank| V5E 0gpio6@ff7d0000rockchip,gpio-bank} W5F 0gpio7@ff7e0000rockchip,gpio-bank~ X5G 0bsgpio8@ff7f0000rockchip,gpio-bank Y5H 0hdmihdmi-cec-c0<lhdmi-cec-c7<lhdmi-ddc <llhdmi-ddc-unwedge <mlpcfg-output-lowJbmpcfg-pull-upUbnpcfg-pull-downbbopcfg-pull-noneqblpcfg-pull-none-12maq~ bpsleepglobal-pwroff<lddrio-pwroff<lddr0-retention<nddr1-retention<nedpedp-hpd< oi2c0i2c0-xfer <llb9i2c1i2c1-xfer <llb!i2c2i2c2-xfer < l lb?i2c3i2c3-xfer <llb"i2c4i2c4-xfer <llb#i2c5i2c5-xfer <llb$i2s0i2s0-bus`<llllllbTlcdclcdc-ctl@<llllbbsdmmcsdmmc-clk<lb sdmmc-cmd<nbsdmmc-cd<nbsdmmc-bus1<nsdmmc-bus4@<nnnnbsdio0sdio0-bus1<nsdio0-bus4@<nnnnsdio0-cmd<nsdio0-clk<lsdio0-cd<nsdio0-wp<nsdio0-pwr<nsdio0-bkpwr<nsdio0-int<nsdio1sdio1-bus1<nsdio1-bus4@<nnnnsdio1-cd<nsdio1-wp<nsdio1-bkpwr<nsdio1-int<nsdio1-cmd<nsdio1-clk<lsdio1-pwr< nemmcemmc-clk<lemmc-cmd<nemmc-pwr< nemmc-bus1<nemmc-bus4@<nnnnemmc-bus8<nnnnnnnnspi0spi0-clk< nbspi0-cs0< nbspi0-tx<nbspi0-rx<nbspi0-cs1<nspi1spi1-clk< nbspi1-cs0< nbspi1-rx<nbspi1-tx<nbspi2spi2-cs1<nspi2-clk<nbspi2-cs0<nb spi2-rx<nbspi2-tx< nbuart0uart0-xfer <nlb%uart0-cts<nuart0-rts<luart1uart1-xfer <n lb&uart1-cts< nuart1-rts< luart2uart2-xfer <nlb'uart3uart3-xfer <nlb(uart3-cts< nuart3-rts< luart4uart4-xfer <nlb)uart4-cts< nuart4-rts< ltsadcotp-gpio< lb/otp-out< lb0pwm0pwm0-pin<lb@pwm1pwm1-pin<lbApwm2pwm2-pin<lbBpwm3pwm3-pin<lbCgmacrgmii-pins<llllpppplll ppllb5rmii-pins<llllllllllspdifspdif-tx< lbSpcfg-output-highbqact8846pmic-vsel<mb=pwr-hold<qb>buttonspwrbtn<nbririr-int<nbtpmicpmic-int<nb<usbhost-vbus-drv<lbuotg-vbus-drv< lbvmemory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacb4gpio-keys gpio-keysdefaultrpower ;tGPIO Key Powerdir-receivergpio-ir-receiver sdefaulttvcc-host-regulatorregulator-fixed :;defaultu vcc_hostvcc-otg-regulatorregulator-fixed :; defaultvvcc_otgsdmmc-regulatorregulator-fixed sdmmc-supplyI2Za2Z :s wbsys-regulatorregulator-fixed sys-supplyILK@aLK@b: #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supply#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplysystem-power-controller#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervalenable-active-highstartup-delay-us