J48@@( @ti,omap4430ti,omap4 +chosenB7/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0aliases?C/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0?H/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0?M/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0ER/ocp/interconnect@48000000/segment@200000/target-module@150000/i2c@0BW/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0B_/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0Bg/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0Bo/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0 w/connector0 /connector1_/ocp/interconnect@4a000000/segment@0/target-module@64000/usbhshost@0/ehci@c00/hub@1/usbether@1cpus+cpu@0arm,cortex-a9cpucpu  'O 5acpu@1arm,cortex-a9cpupmuarm,cortex-a9-pmudebugssinterrupt-controller@48241000arm,cortex-a9-gicH$H$ l2-cache-controller@48242000arm,pl310-cacheH$ ,:local-timer@48240600arm,cortex-a9-twd-timerH$  F  interrupt-controller@48281000ti,omap4-wugen-mpuH( socti,omap-inframpu ti,omap4-mpumpuQdsp ti,omap3-c64iva ti,ivahdivaocpti,omap4-l3-nocsimple-bus+Vl3_main_1l3_main_2l3_main_3DD EF  interconnect@4a300000ti,omap4-l4-wkupsimple-busJ0J0J0 ]aplaia0+$VJ0J1J2segment@0 simple-bus+V`` @@PPtarget-module@4000ti,sysc-omap2ti,sysc@@ ]revsyscg 0fck+ V@counter@0ti,omap-counter32k target-module@6000ti,sysc-omap4ti,sysc`]rev+ V` prm@0ti,omap4-prmsimple-bus  F + V clocks+sys_clkin_ck@110u ti,mux-clock abe_dpll_bypass_clk_mux_ck@108u ti,mux-clock3abe_dpll_refclk_mux_ck@10cu ti,mux-clock 2dbgclk_mux_ckufixed-factor-clockl4_wkup_clk_mux_ck@108u ti,mux-clocksyc_clk_div_ck@100uti,divider-clockusim_ck@1858uti,divider-clockXusim_fclk@1858uti,gate-clockXtrace_clk_div_ckuti,clkdm-gate-clock bandgap_fclk@1888uti,gate-clockclockdomainsemu_sys_clkdmti,clockdomainl4_wkup_cm@1800 ti,omap4-cm+ Vclk@20 ti,clkctrl \uemu_sys_cm@1a00 ti,omap4-cm+ Vclk@20 ti,clkctrl uprm@400#ti,omap4-prm-instti,omap-prm-inst^prm@700#ti,omap4-prm-instti,omap-prm-instprm@f00#ti,omap4-prm-instti,omap-prm-instprm@1b00#ti,omap4-prm-instti,omap-prm-inst@target-module@a000ti,sysc-omap4ti,sysc]rev+ Vscrm@0ti,omap4-scrm clocks+auxclk0_src_gate_ck@310u ti,composite-no-wait-gate-clockauxclk0_src_mux_ck@310uti,composite-mux-clock auxclk0_src_ckuti,composite-clockauxclk0_ck@310uti,divider-clock*auxclk1_src_gate_ck@314u ti,composite-no-wait-gate-clockauxclk1_src_mux_ck@314uti,composite-mux-clock auxclk1_src_ckuti,composite-clockauxclk1_ck@314uti,divider-clock+auxclk2_src_gate_ck@318u ti,composite-no-wait-gate-clockauxclk2_src_mux_ck@318uti,composite-mux-clock auxclk2_src_ckuti,composite-clock auxclk2_ck@318uti,divider-clock ,auxclk3_src_gate_ck@31cu ti,composite-no-wait-gate-clock!auxclk3_src_mux_ck@31cuti,composite-mux-clock "auxclk3_src_ckuti,composite-clock!"#auxclk3_ck@31cuti,divider-clock#-auxclk4_src_gate_ck@320u ti,composite-no-wait-gate-clock $auxclk4_src_mux_ck@320uti,composite-mux-clock  %auxclk4_src_ckuti,composite-clock$%&auxclk4_ck@320uti,divider-clock& .auxclk5_src_gate_ck@324u ti,composite-no-wait-gate-clock$'auxclk5_src_mux_ck@324uti,composite-mux-clock $(auxclk5_src_ckuti,composite-clock'()auxclk5_ck@324uti,divider-clock)$/auxclkreq0_ck@210u ti,mux-clock*+,-./auxclkreq1_ck@214u ti,mux-clock*+,-./auxclkreq2_ck@218u ti,mux-clock*+,-./auxclkreq3_ck@21cu ti,mux-clock*+,-./auxclkreq4_ck@220u ti,mux-clock*+,-./ auxclkreq5_ck@224u ti,mux-clock*+,-./$clockdomainstarget-module@c000ti,sysc-omap4ti,syscctrl_module_wkup ]revsyscg+ Vscm@c000ti,omap4-scm-wkupsegment@10000 simple-bus+xV@@PPtarget-module@0ti,sysc-omap2ti,sysc]revsyscsyssg fckdbclk+ Vgpio@0ti,omap4-gpio F target-module@4000ti,sysc-omap2ti,sysc@@@]revsyscsyss"g fck+ V@wdt@0ti,omap4-wdtti,omap3-wdt FPtarget-module@8000ti,sysc-omap2-timerti,sysc]revsyscsyss' g  fck+ V';timer@0ti,omap3430-timer  fck F%F U etarget-module@c000ti,sysc-omap2ti,sysc]revsyscsyss' g Xfck+ Vkeypad@0ti,omap4-keypad Fx]mputarget-module@e000ti,sysc-omap4ti,syscctrl_module_pad_wkup ]revsyscg+ Vpinmux@40 ti,omap4-padconfpinctrl-single@8+|pinmux_leds_wkpinspinmux_twl6030_wkup_pinsrsegment@20000 simple-bus+V``  00@@PPpptarget-module@0ti,sysc disabled+ Vtarget-module@2000ti,sysc disabled+ V target-module@4000ti,sysc disabled+ V@target-module@6000ti,sysc disabled+0V`p 0interconnect@4a000000ti,omap4-l4-cfgsimple-busJJJ ]aplaia0+TVJJJJ J (J(0J0segment@0 simple-bus+V 00@@PP``pp@  00 ``pp @@PPtarget-module@2000ti,sysc-omap4ti,syscctrl_module_core   ]revsyscg+ V scm@0ti,omap4-scm-coresimple-bus+ Vscm_conf@0syscon+control-phy@300ti,control-phy-usb2]poweracontrol-phy@33cti,control-phy-otghs<]otghs_control`target-module@4000ti,sysc-omap4ti,sysc@]rev+ V@cm1@0ti,omap4-cm1simple-bus + V clocks+extalt_clkin_cku fixed-clockDpad_clks_src_cku fixed-clock0pad_clks_ck@108uti,gate-clock0pad_slimbus_core_clks_cku fixed-clocksecure_32k_clk_src_cku fixed-clockslimbus_src_clku fixed-clock1slimbus_clk@108uti,gate-clock1 sys_32k_cku fixed-clockvirt_12000000_cku fixed-clockvirt_13000000_cku fixed-clock]@ virt_16800000_cku fixed-clockY virt_19200000_cku fixed-clock$ virt_26000000_cku fixed-clock virt_27000000_cku fixed-clock virt_38400000_cku fixed-clockItie_low_clock_cku fixed-clockutmi_phy_clkout_cku fixed-clockxclk60mhsp1_cku fixed-clockZxclk60mhsp2_cku fixed-clock[xclk60motg_cku fixed-clockdpll_abe_ck@1e0uti,omap4-dpll-m4xen-clock234dpll_abe_x2_ck@1f0uti,omap4-dpll-x2-clock45dpll_abe_m2x2_ck@1f0uti,divider-clock56abe_24m_fclkufixed-factor-clock6abe_clk@108uti,divider-clock6dpll_abe_m3x2_ck@1f4uti,divider-clock57core_hsd_byp_clk_mux_ck@12cu ti,mux-clock7,8dpll_core_ck@120uti,omap4-dpll-core-clock8 $,(9dpll_core_x2_ckuti,omap4-dpll-x2-clock9:dpll_core_m6x2_ck@140uti,divider-clock:@dpll_core_m2_ck@130uti,divider-clock90;ddrphy_ckufixed-factor-clock;dpll_core_m5x2_ck@13cuti,divider-clock:<<div_core_ck@100uti,divider-clock<Gdiv_iva_hs_clk@1dcuti,divider-clock<@div_mpu_hs_clk@19cuti,divider-clock<Fdpll_core_m4x2_ck@138uti,divider-clock:8=dll_clk_div_ckufixed-factor-clock=dpll_abe_m2_ck@1f0uti,divider-clock4Jdpll_core_m3x2_gate_ck@134u ti,composite-no-wait-gate-clock:4>dpll_core_m3x2_div_ck@134uti,composite-divider-clock:4?dpll_core_m3x2_ckuti,composite-clock>?dpll_core_m7x2_ck@144uti,divider-clock:Diva_hsd_byp_clk_mux_ck@1acu ti,mux-clock@Adpll_iva_ck@1a0uti,omap4-dpll-clockAUB07Bdpll_iva_x2_ckuti,omap4-dpll-x2-clockBCdpll_iva_m4x2_ck@1b8uti,divider-clockCUD0~Ddpll_iva_m5x2_ck@1bcuti,divider-clockCUE0] Edpll_mpu_ck@160uti,omap4-dpll-clockF`dlhdpll_mpu_m2_ck@170uti,divider-clockpper_hs_clk_div_ckufixed-factor-clock7Kusb_hs_clk_div_ckufixed-factor-clock7Ql3_div_ck@100uti,divider-clockGHl4_div_ck@100uti,divider-clockHlp_clk_div_ckufixed-factor-clock6mpu_periphclkufixed-factor-clockocp_abe_iclk@528uti,divider-clock I(per_abe_24m_fclkufixed-factor-clockJdummy_cku fixed-clockclockdomainsmpuss_cm@300 ti,omap4-cm+ Vclk@20 ti,clkctrl utesla_cm@400 ti,omap4-cm+ Vclk@20 ti,clkctrl u]abe_cm@500 ti,omap4-cm+ Vclk@20 ti,clkctrl luItarget-module@8000ti,sysc-omap4ti,sysc]rev+ V cm2@0ti,omap4-cm2simple-bus + V clocks+per_hsd_byp_clk_mux_ck@14cu ti,mux-clockKLLdpll_per_ck@140uti,omap4-dpll-clockL@DLHMdpll_per_m2_ck@150uti,divider-clockMPUdpll_per_x2_ck@150uti,omap4-dpll-x2-clockMPNdpll_per_m2x2_ck@150uti,divider-clockNPTdpll_per_m3x2_gate_ck@154u ti,composite-no-wait-gate-clockNTOdpll_per_m3x2_div_ck@154uti,composite-divider-clockNTPdpll_per_m3x2_ckuti,composite-clockOPdpll_per_m4x2_ck@158uti,divider-clockNXdpll_per_m5x2_ck@15cuti,divider-clockN\dpll_per_m6x2_ck@160uti,divider-clockN`Sdpll_per_m7x2_ck@164uti,divider-clockNddpll_usb_ck@180uti,omap4-dpll-j-type-clockQRdpll_usb_clkdcoldo_ck@1b4uti,fixed-factor-clockRERdpll_usb_m2_ck@190uti,divider-clockRVducati_clk_mux_ck@100u ti,mux-clockGSfunc_12m_fclkufixed-factor-clockTfunc_24m_clkufixed-factor-clockUfunc_24mc_fclkufixed-factor-clockTfunc_48m_fclk@108uti,divider-clockTfunc_48mc_fclkufixed-factor-clockTfunc_64m_fclk@108uti,divider-clockfunc_96m_fclk@108uti,divider-clockTinit_60m_fclk@104uti,divider-clockVYper_abe_nc_fclk@108uti,divider-clockJsha2md5_fck@15c8uti,gate-clockHusb_phy_cm_clk32k@640uti,gate-clock@bclockdomainsl3_init_clkdmti,clockdomainRl4_ao_cm@600 ti,omap4-cm+ Vclk@20 ti,clkctrl udl3_1_cm@700 ti,omap4-cm+ Vclk@20 ti,clkctrl ul3_2_cm@800 ti,omap4-cm+ Vclk@20 ti,clkctrl uducati_cm@900 ti,omap4-cm + V clk@20 ti,clkctrl ul3_dma_cm@a00 ti,omap4-cm + V clk@20 ti,clkctrl uWl3_emif_cm@b00 ti,omap4-cm + V clk@20 ti,clkctrl ud2d_cm@c00 ti,omap4-cm + V clk@20 ti,clkctrl ucl4_cfg_cm@d00 ti,omap4-cm + V clk@20 ti,clkctrl uel3_instr_cm@e00 ti,omap4-cm+ Vclk@20 ti,clkctrl $uivahd_cm@f00 ti,omap4-cm+ Vclk@20 ti,clkctrl uiss_cm@1000 ti,omap4-cm+ Vclk@20 ti,clkctrl ull3_dss_cm@1100 ti,omap4-cm+ Vclk@20 ti,clkctrl ul3_gfx_cm@1200 ti,omap4-cm+ Vclk@20 ti,clkctrl ul3_init_cm@1300 ti,omap4-cm+ Vclk@20 ti,clkctrl uXl4_per_cm@1400 ti,omap4-cm+ Vclock@20ti,clkctrl-l4-perti,clkctrl Dumclock@1a0 ti,clkctrl-l4-secureti,clkctrl<uytarget-module@56000ti,sysc-omap2ti,sysc``,`(]revsyscsyss# ` g Wfck+ V`dma-controller@0ti,omap4430-sdmati,omap-sdma0F  ny ztarget-module@58000ti,sysc-omap2ti,sysc]revsyscsyss#`g Xfck+ VPhsi@0 ti,omap4-hsi@P]sysgdd Xhsi_fck FGgdd_mpu+ V@hsi-port@2000ti,omap4-hsi-port (]txrx FChsi-port@3000ti,omap4-hsi-port08]txrx FDtarget-module@5e000ti,sysc disabled+ V target-module@62000ti,sysc-omap2ti,sysc usb_tll_hs   ]revsyscsyss g XHfck+ V usbhstll@0 ti,usbhs-tll FNtarget-module@64000ti,sysc-omap4ti,sysc usb_host_hs@@@]revsyscsyss`g X8fck+ V@usbhshost@0ti,usbhs-host+ V YZ[3refclk_60m_intrefclk_60m_ext_p1refclk_60m_ext_p2 ehci-phyohci@800ti,ohci-omap3 FLehci@c00 ti,ehci-omap  FM\+hub@1 usb424,9514+usbether@1 usb424,ec00target-module@66000ti,sysc-omap2ti,sysc```]revsyscsyss g ]fck^rstctrl+ V`mmu@0ti,omap4-iommu Fsegment@80000 simple-bus+V      @@PP``pp` `p p        target-module@29000ti,sysc disabled+ Vtarget-module@2b000ti,sysc-omap2ti,sysc]revsyscsyss `g X@fck+ Vusb_otg_hs@0ti,omap4-musbF\]mcdma__ usb2-phy `%42target-module@2d000ti,sysc-omap2ti,sysc]revsyscsyss g Xfck+ Vocp2scp@0ti,omap-ocp2scp+ Vusb2phy@80 ti,omap-usb2Xabwkupclk:_target-module@36000ti,sysc-omap2ti,sysc```]revsyscsyssg cfck+ V`target-module@4d000ti,sysc-omap2ti,sysc]revsyscsyssg cfck+ Vtarget-module@59000ti,sysc-omap4-srti,sysc8]syscg dfck+ Vsmartreflex@0ti,omap4-smartreflex-mpu Ftarget-module@5b000ti,sysc-omap4-srti,sysc8]syscg dfck+ Vsmartreflex@0ti,omap4-smartreflex-iva Fftarget-module@5d000ti,sysc-omap4-srti,sysc8]syscg dfck+ Vsmartreflex@0ti,omap4-smartreflex-core Ftarget-module@60000ti,sysc disabled+ Vtarget-module@74000ti,sysc-omap4ti,sysc@@ ]revsysc g efck+ V@mailbox@0ti,omap4-mailbox FEQcmbox_ipu u mbox_dsp u target-module@76000ti,sysc-omap2ti,sysc```]revsyscsyss g efck+ V`spinlock@0ti,omap4-hwspinlocksegment@100000 simple-bus+`V  00target-module@0ti,sysc-omap4ti,syscctrl_module_pad_core ]revsyscg+ Vpinmux@40 ti,omap4-padconfpinctrl-single@+|defaultfghijnpinmux_mcpdm_pins(pinmux_twl6040_pins`tpinmux_mcbsp1_pins pinmux_dss_dpi_pins"$&(*,.0246tvxz|~fpinmux_tfp410_pinsDgpinmux_dss_hdmi_pinsZ\^hpinmux_tpd12s015_pins"HX ipinmux_hsusbb1_pins`           jpinmux_i2c1_pinsppinmux_i2c2_pinsxpinmux_i2c3_pinsopinmux_i2c4_pinspinmux_wl12xx_gpio &,02pinmux_wl12xx_pins@8:  }pinmux_button_pinspinmux_twl6030_pins^Aqomap4_padconf_global@5a0sysconsimple-busp+ Vpkpbias_regulator@60ti,pbias-omap4ti,pbias-omap`kpbias_mmc_omap4pbias_mmc_omap4w@-{target-module@2000ti,sysc disabled+ V target-module@8000ti,sysc disabled+ Vtarget-module@a000ti,sysc-omap4ti,sysc ]revsysc ` g lfck+ Vsegment@180000 simple-bus+segment@200000 simple-bus+hV!!  @ @P P` `p p ! 0!0  !!`!`p!p@!@P!P!!""`"`p"p""""!!target-module@4000ti,sysc disabled+ V@target-module@6000ti,sysc disabled+ V`target-module@a000ti,sysc disabled+ Vtarget-module@c000ti,sysc disabled+ Vtarget-module@10000ti,sysc disabled+ Vtarget-module@12000ti,sysc disabled+ V target-module@14000ti,sysc disabled+ V@target-module@16000ti,sysc disabled+ V`target-module@18000ti,sysc disabled+ Vtarget-module@1c000ti,sysc disabled+ Vtarget-module@1e000ti,sysc disabled+ Vtarget-module@20000ti,sysc disabled+ Vtarget-module@26000ti,sysc disabled+ V`target-module@28000ti,sysc disabled+ Vtarget-module@2a000ti,sysc disabled+ Vsegment@280000 simple-bus+segment@300000 simple-bus+V042@@2@ `2`p2p2232 2@target-module@0ti,sysc disabled+xV@@@ ``pp @interconnect@48000000ti,omap4-l4-persimple-bus0HHHHHH]aplaia0ia1ia2ia3+VH H segment@0 simple-bus+V  00@@PP``ppPP``pp  00 ` ` p p``pp``pp             @ @ ` ` @     0 0 @ @ P P        P P ` `  0 0 P Ptarget-module@20000ti,sysc-omap2ti,syscPTX]revsyscsyssg m0fck+ Vserial@0ti,omap4-uart FJlJntarget-module@32000ti,sysc-omap2-timerti,sysc   ]revsyscsyss' g mfck+ V timer@0ti,omap3430-timer mfck F&target-module@34000ti,sysc-omap4-timerti,sysc@@ ]revsyscg m fck+ V@timer@0ti,omap4430-timer m fck F'target-module@36000ti,sysc-omap4-timerti,sysc`` ]revsyscg m(fck+ V`timer@0ti,omap4430-timer m(fck F(target-module@3e000ti,sysc-omap4-timerti,sysc ]revsyscg m0fck+ Vtimer@0ti,omap4430-timer m0fck F-target-module@40000ti,sysc disabled+ Vtarget-module@55000ti,sysc-omap2ti,syscPPQ]revsyscsyssgm@m@ fckdbclk+ VPgpio@0ti,omap4-gpio F target-module@57000ti,sysc-omap2ti,syscppq]revsyscsyssgmHmH fckdbclk+ Vpgpio@0ti,omap4-gpio F target-module@59000ti,sysc-omap2ti,sysc]revsyscsyssgmPmP fckdbclk+ Vgpio@0ti,omap4-gpio F  utarget-module@5b000ti,sysc-omap2ti,sysc]revsyscsyssgmXmX fckdbclk+ Vgpio@0ti,omap4-gpio F! target-module@5d000ti,sysc-omap2ti,sysc]revsyscsyssgm`m` fckdbclk+ Vgpio@0ti,omap4-gpio F" target-module@60000ti,sysc-omap2ti,sysc]revsyscsyssg mfck+ Vi2c@0 ti,omap4-i2c F=+defaultoeeprom@50 ti,eepromPtarget-module@6a000ti,sysc-omap2ti,syscPTX]revsyscsyssg m fck+ Vserial@0ti,omap4-uart FHltarget-module@6c000ti,sysc-omap2ti,syscPTX]revsyscsyssg m(fck+ Vserial@0ti,omap4-uart FIlIntarget-module@6e000ti,sysc-omap2ti,syscPTX]revsyscsyssg m8fck+ Vserial@0ti,omap4-uart FFlFntarget-module@70000ti,sysc-omap2ti,sysc]revsyscsyssg mfck+ Vi2c@0 ti,omap4-i2c F8+defaultptwl@48H F ti,twl6030defaultqrrtcti,twl4030-rtcF regulator-vaux1ti,twl6030-vaux1B@-regulator-vaux2ti,twl6030-vaux2O*regulator-vaux3ti,twl6030-vaux3B@-regulator-vmmcti,twl6030-vmmcO-|regulator-vppti,twl6030-vppw@&%regulator-vusimti,twl6030-vusimO,@ regulator-vdacti,twl6030-vdacregulator-vanati,twl6030-vanaregulator-vcxioti,twl6030-vcxio)regulator-vusbti,twl6030-vusbsregulator-v1v8ti,twl6030-v1v8)vregulator-v2v1ti,twl6030-v2v1)wusb-comparatorti,twl6030-usbF =spwmti,twl6030-pwmHpwmledti,twl6030-pwmledHgpadcti,twl6030-gpadcFStwl@4b ti,twl6040uKdefaultt Fw euvvwtarget-module@72000ti,sysc-omap2ti,sysc   ]revsyscsyssg mfck+ V i2c@0 ti,omap4-i2c F9+defaultxtarget-module@76000ti,sysc-omap4ti,sysc`` ]revsyscg mfck+ V`target-module@78000ti,sysc-omap2ti,sysc]revsyscsyss g m8fck+ Velm@0ti,am3352-elm  F disabledtarget-module@86000ti,sysc-omap2-timerti,sysc```]revsyscsyss' g mfck+ V`timer@0ti,omap3430-timer mfck F.target-module@88000ti,sysc-omap4-timerti,sysc ]revsyscg mfck+ Vtimer@0ti,omap4430-timer mfck F/target-module@90000ti,sysc-omap2ti,sysc   ]revsyscg y fck+ V rng@0 ti,omap4-rng  F4target-module@96000ti,sysc-omap2ti,sysc `]sysc g mfck+ V `mcbsp@0ti,omap4-mcbsp]mpu Fcommonzz txrx disabledtarget-module@98000ti,sysc-omap4ti,sysc   ]revsyscg mfck+ V spi@0ti,omap4-mcspi FA+@z#z$z%z&z'z(z)z* tx0rx0tx1rx1tx2rx2tx3rx3target-module@9a000ti,sysc-omap4ti,sysc   ]revsyscg mfck+ V spi@0ti,omap4-mcspi FB+ z+z,z-z.tx0rx0tx1rx1target-module@9c000ti,sysc-omap4ti,sysc   ]revsysc`g Xfck+ V mmc@0ti,omap4-hsmmc FSz=z>txrx{| target-module@9e000ti,sysc disabled+ V target-module@a2000ti,sysc disabled+ V target-module@a4000ti,sysc disabled+V @ Ptarget-module@a5000ti,sysc-omap2ti,sysc P0 P4 P8]revsyscsyssg yfck+ V Pdes@0 ti,omap4-des FRzuzttxrxtarget-module@a8000ti,sysc disabled+ V @target-module@ad000ti,sysc-omap4ti,sysc   ]revsysc`g mfck+ V mmc@0ti,omap4-hsmmc F^zMzNtxrx disabledtarget-module@b0000ti,sysc disabled+ V target-module@b2000ti,sysc-omap2ti,sysc   ]revsyscsyss' mhfck+ V 1w@0 ti,omap3-1w F:target-module@b4000ti,sysc-omap4ti,sysc @ @ ]revsysc`g Xfck+ V @mmc@0ti,omap4-hsmmc FVz/z0txrx disabledtarget-module@b8000ti,sysc-omap4ti,sysc   ]revsyscg mfck+ V spi@0ti,omap4-mcspi F[+zztx0rx0target-module@ba000ti,sysc-omap4ti,sysc   ]revsyscg mfck+ V spi@0ti,omap4-mcspi F0+zFzGtx0rx0target-module@d1000ti,sysc-omap4ti,sysc   ]revsysc`g mfck+ V mmc@0ti,omap4-hsmmc F`z9z:txrx disabledtarget-module@d5000ti,sysc-omap4ti,sysc P P ]revsysc`g m@fck+ V Pmmc@0ti,omap4-hsmmc F;z;z<txrxdefault}~;n !+wlcore@2 ti,wl1271n: irqwakeup4Isegment@200000 simple-bus+V55target-module@150000ti,sysc-omap2ti,sysc]revsyscsyssg mfck+ Vi2c@0 ti,omap4-i2c F>+defaultinterconnect@40100000ti,omap4-l4-abesimple-bus@@]laap+V@IIsegment@0 simple-bus+0V  00@@PP``pp  00      IIIII I I0I0I@I@IPIPI`I`IpIpIIIIIIIIIIIIIIIII I I0I0IIIIIIIIIIIIIIIIIIIII I I I I I I I III I target-module@22000ti,sysc-omap2ti,sysc ]sysc g I(fck+V I I mcbsp@0ti,omap4-mcbspI ]mpudma Fcommonz!z"txrxokaydefaulttarget-module@24000ti,sysc-omap2ti,sysc@]sysc g I0fck+V@I@I@mcbsp@0ti,omap4-mcbspI@]mpudma Fcommonzztxrx disabledtarget-module@26000ti,sysc-omap2ti,sysc`]sysc g I8fck+V`I`I`mcbsp@0ti,omap4-mcbspI`]mpudma Fcommonzztxrx disabledtarget-module@28000ti,sysc-mcaspti,sysc ]revsyscg I fck+VIItarget-module@2a000ti,sysc disabled+VIItarget-module@2e000ti,sysc-omap4ti,sysc ]revsyscg Ifck+VIIdmic@0ti,omap4-dmicI]mpudma FrzCup_link disabledtarget-module@30000ti,sysc-omap2ti,sysc]revsyscsyss"g Ihfck+VIIwdt@0ti,omap4-wdtti,omap3-wdt FPtarget-module@32000ti,sysc-omap4ti,sysc   ]revsyscg Ifck+V I I okaydefaultmcpdm@0ti,omap4-mcpdmI ]mpudma FpzAzBup_linkdn_linkpdmclktarget-module@38000ti,sysc-omap4-timerti,sysc ]revsyscg IHfck+VIItimer@0ti,omap4430-timerI IHfck F)Htarget-module@3a000ti,sysc-omap4-timerti,sysc ]revsyscg IPfck+VIItimer@0ti,omap4430-timerI IPfck F*Htarget-module@3c000ti,sysc-omap4-timerti,sysc ]revsyscg IXfck+VIItimer@0ti,omap4430-timerI IXfck F+Htarget-module@3e000ti,sysc-omap4-timerti,sysc ]revsyscg I`fck+VIItimer@0ti,omap4430-timerI I`fck F,Htarget-module@80000ti,sysc disabled+VIItarget-module@a0000ti,sysc disabled+V I I target-module@c0000ti,sysc disabled+V I I target-module@f1000ti,sysc-omap4ti,sysc ]revsysc` g Ifck+VIIsram@40304000 mmio-sram@0@gpmc@50000000ti,omap4430-gpmcP+ FzrxtxUagpmcsHfck target-module@52000000ti,sysc-omap4ti,syscissRR ]revsysc`g lfck+ VRtarget-module@55082000ti,sysc-omap2ti,syscU U U ]revsyscsyss g fckrstctrl VU +mmu@0ti,omap4-iommu Fdtarget-module@4012c000ti,sysc-omap4ti,sysc@@ ]revsyscg I@fck+V@IIdmm@4e000000 ti,omap4-dmmN Fqdmmemif@4c000000 ti,emif-4dL Fnemif1semif@4d000000 ti,emif-4dM Foemif2starget-module@4b501000ti,sysc-omap2ti,syscKPKPKP]revsyscsyssg yfck+ VKPaes@0 ti,omap4-aes FUzozntxrxtarget-module@4b701000ti,sysc-omap2ti,syscKpKpKp]revsyscsyssg yfck+ VKpaes@0 ti,omap4-aes F@zrzqtxrxtarget-module@4b100000ti,sysc-omap3-shamti,syscKKK]revsyscsyss g y(fck+ VKsham@0ti,omap4-sham F3zwrxregulator-abb-mpu ti,abb-v2abb_mpu+2%okayJ0{J0`]base-addressint-addressx5O1regulator-abb-iva ti,abb-v2abb_iva+2% disabledJ0{J0`]base-addressint-addresstarget-module@56000000ti,sysc-omap4ti,syscVV ]revsysc`g fck+ VVtarget-module@58000000ti,sysc-omap2ti,syscXX ]revsyss0 fckhdmi_clksys_clktv_clk+ VXdss@0 ti,omap4-dssok fck+ Vtarget-module@1000ti,sysc-omap2ti,sysc]revsyscsyss g `  fcksys_clk+ Vdispc@0ti,omap4-dispc F fcktarget-module@2000ti,sysc-omap2ti,sysc   ]revsyscsyss g  fcksys_clk+ V encoder@0 disabledHfckicktarget-module@3000ti,sysc-omap2ti,sysc0]rev sys_clk+ V0encoder@0ti,omap4-venc disabled fcktarget-module@4000ti,sysc-omap2ti,sysc@@@]revsyscsyss g+ V@encoder@0 ti,omap4-dsi@ ]protophypll F5 disabled  fcksys_clktarget-module@5000ti,sysc-omap2ti,syscPPP]revsyscsyss g+ VPencoder@0 ti,omap4-dsi@ ]protophypll FTok  fcksys_clkAtarget-module@6000ti,sysc-omap4ti,sysc`` ]revsyscg  fckdss_clk+ V` encoder@0ti,omap4-hdmi ]wppllphycore Feok  fcksys_clkzL audio_txLportendpointXportendpointXhbandgap@4a002260J"`J#,ti,omap4430-bandgapsthermal-zonescpu_thermalN tripscpu_alertpassivecpu_critH criticalcooling-mapsmap0 lpddr2#Elpida,ECB240ABACNjedec,lpddr2-s4 !-=JWcp}lpddr2-timings@0jedec,lpddr2-timingsׄRFP:'LLL:|P_~@B@ p plpddr2-timings@1jedec,lpddr2-timings RFP:''LL:|P_~@B@ p pmemory@80000000memory@leds gpio-ledsdefaultheartbeat pandaboard::status1 & ,heartbeatmmc pandaboard::status2 & ,mmc0gpio_keys gpio-keysdefaultbuttonS2 button S2 &u B Msoundti,abe-twl6040 [PandaBoard dI q z Headset StereophoneHSOLHeadset StereophoneHSORExt SpkHFLExt SpkHFRLine OutAUXLLine OutAUXRHSMICHeadset MicHeadset MicHeadset Mic BiasAFMLLine InAFMRLine Inhsusb1_power_regregulator-fixed hsusb1_vbus2Z2Z q p) hsusb1_phyusb-nop-xceiv : - main_clk$\wl12xx_vmmcdefaultregulator-fixedvwl1271w@w@ q  p~encoder0 ti,tfp410 ports+port@0endpointXport@1endpointXconnector0dvi-connector dvi  portendpointXencoder1 ti,tpd12s015$ & ports+port@0endpointXport@1endpointXconnector1hdmi-connector hdmiaportendpointX compatibleinterrupt-parent#address-cells#size-cellsstdout-pathi2c0i2c1i2c2i2c3serial0serial1serial2serial3display0display1ethernetdevice_typenext-level-cacheregclocksclock-namesclock-latencyoperating-points#cooling-cellsphandleti,hwmodsinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptssramrangesreg-namesti,sysc-sidle#clock-cellsti,index-starts-at-oneti,bit-shiftclock-multclock-divti,max-divti,dividers#reset-cellsti,sysc-maskti,syss-maskti,gpio-always-ongpio-controller#gpio-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parents#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsstatusclock-frequencyti,autoidle-shiftti,invert-autoidle-bitti,index-power-of-twoassigned-clock-ratesti,clock-divti,clock-multti,sysc-midle#dma-cellsdma-channelsdma-requestsinterrupt-namesport1-moderemote-wakeup-connectedphysresetsreset-names#iommu-cellsusb-phyphy-namesmultipointnum-epsram-bitsctrl-moduleinterface-typepower#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rx#hwlock-cellspinctrl-namespinctrl-0sysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,sysc-delay-usinterrupts-extendedti,timer-pwmregulator-always-onusb-supply#pwm-cells#io-channel-cellsti,audpwron-gpiovio-supplyv2v1-supplyenable-active-highti,buffer-sizedmasdma-namesti,spi-num-csti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthnon-removablecap-power-off-cardref-clock-frequencyti,timer-dspgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initti,iommu-bus-err-backphy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertcs1-useddevice-handleti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infovdd-supplyvdda-supplyremote-endpointdata-lines#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorscoefficientstemperaturehysteresistripcooling-devicedensityio-widthtRPab-min-tcktRCD-min-tcktWR-min-tcktRASmin-min-tcktRRD-min-tcktWTR-min-tcktXP-min-tcktRTP-min-tcktCKE-min-tcktCKESR-min-tcktFAW-min-tckmin-freqmax-freqtRPabtRCDtWRtRAS-mintRRDtWTRtXPtRTPtCKESRtDQSCK-maxtFAWtZQCStZQCLtZQinittRAS-max-nstDQSCK-max-deratedlabelgpioslinux,default-triggerlinux,codewakeup-sourceti,modelti,mclk-freqti,mcpdmti,twl6040ti,audio-routingstartup-delay-usregulator-boot-onreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-bus