28(>%ti,omap3430-sdpti,omap3430ti,omap3 +7TI OMAP3430 SDPchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000cpus+cpu@0arm,cortex-a8dcpupt{cpupmu@54000000arm,cortex-a8-pmupTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busph +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busp + pinmux@30 ti,omap3-padconfpinctrl-singlep08+pinmux_twl4030_pins5AIscm_conf@270sysconsimple-buspp0+ p0Ipbias_regulator@2b0ti,pbias-omap3ti,pbias-omappQpbias_mmc_omap2430Xpbias_mmc_omap2430gw@-Iclocks+mcbsp5_mux_fck@68ti,composite-mux-clocktphImcbsp5_fckti,composite-clocktImcbsp1_mux_fck@4ti,composite-mux-clocktpI mcbsp1_fckti,composite-clockt Imcbsp2_mux_fck@4ti,composite-mux-clockt pI mcbsp2_fckti,composite-clockt Imcbsp3_mux_fck@68ti,composite-mux-clockt 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8Idpll4_m5_ck@f40ti,divider-clockt?p@I3dpll4_m5x2_mul_ckti,fixed-factor-clockt3+8I4dpll4_m5x2_ck@d00ti,gate-clockt4p 8Ijdpll4_m6_ck@1140ti,divider-clockt?p@I5dpll4_m6x2_mul_ckfixed-factor-clockt5I6dpll4_m6x2_ck@d00ti,gate-clockt6p I7emu_per_alwon_ckfixed-factor-clockt7Icclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clockt&p pI9clkout2_src_mux_ck@d70ti,composite-mux-clockt&*8p pI:clkout2_src_ckti,composite-clockt9:I;sys_clkout2@d70ti,divider-clockt;@p pKmpu_ckfixed-factor-clockt<I=arm_fck@924ti,divider-clockt=p $emu_mpu_alwon_ckfixed-factor-clockt=Idl3_ick@a40ti,divider-clockt&p @I>l4_ick@a40ti,divider-clockt>p @I?rm_ick@c40ti,divider-clockt?p @gpt10_gate_fck@a00ti,composite-gate-clockt p IAgpt10_mux_fck@a40ti,composite-mux-clockt@p @IBgpt10_fckti,composite-clocktABgpt11_gate_fck@a00ti,composite-gate-clockt p ICgpt11_mux_fck@a40ti,composite-mux-clockt@p @IDgpt11_fckti,composite-clocktCDcore_96m_fckfixed-factor-clocktEImmchs2_fck@a00ti,wait-gate-clocktp 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-points-v2interruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinslinux,mtd-namebank-widthgpmc,mux-add-datagpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenlabelti,nand-ecc-optnand-bus-widthgpmc,device-widthmultipointnum-epsram-bitsiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensors